670 lines
17 KiB
C
670 lines
17 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_hw_training.h"
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#include "xor.h"
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#include "xor_regs.h"
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static void ddr3_flush_l1_line(u32 line);
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extern u32 pbs_pattern[2][LEN_16BIT_PBS_PATTERN];
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extern u32 pbs_pattern_32b[2][LEN_PBS_PATTERN];
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#if defined(MV88F78X60)
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extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
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#endif
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extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
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#if defined(MV88F78X60) || defined(MV88F672X)
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/* PBS locked dq (per pup) */
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u32 pbs_locked_dq[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
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u32 pbs_locked_dm[MAX_PUP_NUM] = { 0 };
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u32 pbs_locked_value[MAX_PUP_NUM][DQ_NUM] = { { 0 } };
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int per_bit_data[MAX_PUP_NUM][DQ_NUM];
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#endif
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static u32 sdram_data[LEN_KILLER_PATTERN] __aligned(32) = { 0 };
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static struct crc_dma_desc dma_desc __aligned(32) = { 0 };
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#define XOR_TIMEOUT 0x8000000
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struct xor_channel_t {
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struct crc_dma_desc *desc;
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unsigned long desc_phys_addr;
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};
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#define XOR_CAUSE_DONE_MASK(chan) ((0x1 | 0x2) << (chan * 16))
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void xor_waiton_eng(int chan)
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{
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int timeout;
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timeout = 0;
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while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) &
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XOR_CAUSE_DONE_MASK(XOR_CHAN(chan)))) {
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if (timeout > XOR_TIMEOUT)
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goto timeout;
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timeout++;
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}
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timeout = 0;
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while (mv_xor_state_get(chan) != MV_IDLE) {
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if (timeout > XOR_TIMEOUT)
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goto timeout;
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timeout++;
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}
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/* Clear int */
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reg_write(XOR_CAUSE_REG(XOR_UNIT(chan)),
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~(XOR_CAUSE_DONE_MASK(XOR_CHAN(chan))));
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timeout:
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return;
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}
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static int special_compare_pattern(u32 uj)
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{
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if ((uj == 30) || (uj == 31) || (uj == 61) || (uj == 62) ||
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(uj == 93) || (uj == 94) || (uj == 126) || (uj == 127))
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return 1;
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return 0;
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}
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/*
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* Compare code extracted as its used by multiple functions. This
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* reduces code-size and makes it easier to maintain it. Additionally
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* the code is not indented that much and therefore easier to read.
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*/
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static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern,
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u32 pup_groups, int debug_dqs)
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{
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u32 val;
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u32 uk;
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u32 var1;
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u32 var2;
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__maybe_unused u32 dq;
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if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) {
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for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
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val = CMP_BYTE_SHIFT * uk;
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var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
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var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
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if (var1 != var2) {
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*pup |= (1 << (uk + (PUP_NUM_32BIT *
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(uj % pup_groups))));
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#ifdef MV_DEBUG_DQS
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if (!debug_dqs)
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continue;
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for (dq = 0; dq < DQ_NUM; dq++) {
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val = uk + (PUP_NUM_32BIT *
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(uj % pup_groups));
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if (((var1 >> dq) & 0x1) !=
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((var2 >> dq) & 0x1))
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per_bit_data[val][dq] = 1;
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else
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per_bit_data[val][dq] = 0;
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}
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#endif
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}
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}
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}
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}
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static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern)
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{
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u32 val;
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u32 uk;
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u32 var1;
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u32 var2;
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if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) {
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/* Found error */
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for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
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val = CMP_BYTE_SHIFT * uk;
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var1 = (sdram_data[uj] >> val) & CMP_BYTE_MASK;
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var2 = (pattern[uj] >> val) & CMP_BYTE_MASK;
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if (var1 != var2)
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*pup |= (1 << (uk % PUP_NUM_16BIT));
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}
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}
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}
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/*
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* Name: ddr3_sdram_compare
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* Desc: Execute compare per PUP
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* Args: unlock_pup Bit array of the unlock pups
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* new_locked_pup Output bit array of the pups with failed compare
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* pattern Pattern to compare
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* pattern_len Length of pattern (in bytes)
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* sdram_offset offset address to the SDRAM
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* write write to the SDRAM before read
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* mask compare pattern with mask;
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* mask_pattern Mask to compare pattern
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*
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 pattern_len, u32 sdram_offset, int write,
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int mask, u32 *mask_pattern,
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int special_compare)
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{
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u32 uj;
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__maybe_unused u32 pup_groups;
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__maybe_unused u32 dq;
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#if !defined(MV88F67XX)
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if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
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pup_groups = 2;
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else
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pup_groups = 1;
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#endif
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ddr3_reset_phy_read_fifo();
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/* Check if need to write to sdram before read */
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if (write == 1)
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ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
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ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
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/* Compare read result to write */
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for (uj = 0; uj < pattern_len; uj++) {
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if (special_compare && special_compare_pattern(uj))
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continue;
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#if defined(MV88F78X60) || defined(MV88F672X)
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compare_pattern_v1(uj, new_locked_pup, pattern, pup_groups, 1);
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#elif defined(MV88F67XX)
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compare_pattern_v2(uj, new_locked_pup, pattern);
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#endif
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}
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return MV_OK;
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}
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#if defined(MV88F78X60) || defined(MV88F672X)
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/*
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* Name: ddr3_sdram_dm_compare
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* Desc: Execute compare per PUP
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* Args: unlock_pup Bit array of the unlock pups
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* new_locked_pup Output bit array of the pups with failed compare
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* pattern Pattern to compare
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* pattern_len Length of pattern (in bytes)
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* sdram_offset offset address to the SDRAM
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* write write to the SDRAM before read
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* mask compare pattern with mask;
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* mask_pattern Mask to compare pattern
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*
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 sdram_offset)
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{
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u32 uj, uk, var1, var2, pup_groups;
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u32 val;
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u32 pup = 0;
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if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
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pup_groups = 2;
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else
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pup_groups = 1;
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ddr3_dram_sram_burst((u32)pattern, SDRAM_PBS_TX_OFFS,
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LEN_PBS_PATTERN);
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ddr3_dram_sram_burst(SDRAM_PBS_TX_OFFS, (u32)sdram_data,
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LEN_PBS_PATTERN);
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/* Validate the correctness of the results */
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for (uj = 0; uj < LEN_PBS_PATTERN; uj++)
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compare_pattern_v1(uj, &pup, pattern, pup_groups, 0);
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/* Test the DM Signals */
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*(u32 *)(SDRAM_PBS_TX_OFFS + 0x10) = 0x12345678;
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*(u32 *)(SDRAM_PBS_TX_OFFS + 0x14) = 0x12345678;
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sdram_data[0] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x10);
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sdram_data[1] = *(u32 *)(SDRAM_PBS_TX_OFFS + 0x14);
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for (uj = 0; uj < 2; uj++) {
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if (((sdram_data[uj]) != (pattern[uj])) &&
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(*new_locked_pup != 0xFF)) {
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for (uk = 0; uk < PUP_NUM_32BIT; uk++) {
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val = CMP_BYTE_SHIFT * uk;
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var1 = ((sdram_data[uj] >> val) & CMP_BYTE_MASK);
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var2 = ((pattern[uj] >> val) & CMP_BYTE_MASK);
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if (var1 != var2) {
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*new_locked_pup |= (1 << (uk +
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(PUP_NUM_32BIT * (uj % pup_groups))));
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*new_locked_pup |= pup;
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}
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}
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}
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}
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return MV_OK;
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}
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/*
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* Name: ddr3_sdram_pbs_compare
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* Desc: Execute SRAM compare per PUP and DQ.
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* Args: pup_locked bit array of locked pups
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* is_tx Indicate whether Rx or Tx
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* pbs_pattern_idx Index of PBS pattern
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* pbs_curr_val The PBS value
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* pbs_lock_val The value to set to locked PBS
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* skew_array Global array to update with the compare results
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* ai_unlock_pup_dq_array bit array of the locked / unlocked pups per dq.
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked,
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int is_tx, u32 pbs_pattern_idx,
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u32 pbs_curr_val, u32 pbs_lock_val,
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u32 *skew_array, u8 *unlock_pup_dq_array,
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u32 ecc)
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{
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/* bit array failed dq per pup for current compare */
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u32 pbs_write_pup[DQ_NUM] = { 0 };
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u32 update_pup; /* pup as HW convention */
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u32 max_pup; /* maximal pup index */
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u32 pup_addr;
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u32 ui, dq, pup;
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int var1, var2;
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u32 sdram_offset, pup_groups, tmp_pup;
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u32 *pattern_ptr;
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u32 val;
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/* Choose pattern */
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switch (dram_info->ddr_width) {
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#if defined(MV88F672X)
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case 16:
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pattern_ptr = (u32 *)&pbs_pattern[pbs_pattern_idx];
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break;
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#endif
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case 32:
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pattern_ptr = (u32 *)&pbs_pattern_32b[pbs_pattern_idx];
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break;
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#if defined(MV88F78X60)
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case 64:
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pattern_ptr = (u32 *)&pbs_pattern_64b[pbs_pattern_idx];
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break;
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#endif
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default:
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return MV_FAIL;
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}
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max_pup = dram_info->num_of_std_pups;
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sdram_offset = SDRAM_PBS_I_OFFS + pbs_pattern_idx * SDRAM_PBS_NEXT_OFFS;
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if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
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pup_groups = 2;
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else
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pup_groups = 1;
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ddr3_reset_phy_read_fifo();
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/* Check if need to write to sdram before read */
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if (is_tx == 1) {
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ddr3_dram_sram_burst((u32)pattern_ptr, sdram_offset,
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LEN_PBS_PATTERN);
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}
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ddr3_dram_sram_read(sdram_offset, (u32)sdram_data, LEN_PBS_PATTERN);
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/* Compare read result to write */
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for (ui = 0; ui < LEN_PBS_PATTERN; ui++) {
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if ((sdram_data[ui]) != (pattern_ptr[ui])) {
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/* found error */
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/* error in low pup group */
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for (pup = 0; pup < PUP_NUM_32BIT; pup++) {
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val = CMP_BYTE_SHIFT * pup;
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var1 = ((sdram_data[ui] >> val) &
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CMP_BYTE_MASK);
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var2 = ((pattern_ptr[ui] >> val) &
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CMP_BYTE_MASK);
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if (var1 != var2) {
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if (dram_info->ddr_width > 16) {
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tmp_pup = (pup + PUP_NUM_32BIT *
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(ui % pup_groups));
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} else {
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tmp_pup = (pup % PUP_NUM_16BIT);
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}
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update_pup = (1 << tmp_pup);
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if (ecc && (update_pup != 0x1))
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continue;
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/*
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* Pup is failed - Go over all DQs and
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* look for failures
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*/
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for (dq = 0; dq < DQ_NUM; dq++) {
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val = tmp_pup * (1 - ecc) +
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ecc * ECC_PUP;
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if (((var1 >> dq) & 0x1) !=
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((var2 >> dq) & 0x1)) {
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if (pbs_locked_dq[val][dq] == 1 &&
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pbs_locked_value[val][dq] != pbs_curr_val)
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continue;
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/*
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* Activate write to
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* update PBS to
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* pbs_lock_val
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*/
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pbs_write_pup[dq] |=
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update_pup;
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/*
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* Update the
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* unlock_pup_dq_array
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*/
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unlock_pup_dq_array[dq] &=
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~update_pup;
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/*
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* Lock PBS value for
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* failed bits in
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* compare operation
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*/
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skew_array[tmp_pup * DQ_NUM + dq] =
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pbs_curr_val;
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}
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}
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}
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}
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}
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}
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pup_addr = (is_tx == 1) ? PUP_PBS_TX : PUP_PBS_RX;
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/* Set last failed bits PBS to min / max pbs value */
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for (dq = 0; dq < DQ_NUM; dq++) {
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for (pup = 0; pup < max_pup; pup++) {
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if (pbs_write_pup[dq] & (1 << pup)) {
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val = pup * (1 - ecc) + ecc * ECC_PUP;
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if (pbs_locked_dq[val][dq] == 1 &&
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pbs_locked_value[val][dq] != pbs_curr_val)
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continue;
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/* Mark the dq as locked */
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pbs_locked_dq[val][dq] = 1;
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pbs_locked_value[val][dq] = pbs_curr_val;
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ddr3_write_pup_reg(pup_addr +
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pbs_dq_mapping[val][dq],
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CS0, val, 0, pbs_lock_val);
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}
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}
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}
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return MV_OK;
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}
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#endif
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/*
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* Name: ddr3_sdram_direct_compare
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* Desc: Execute compare per PUP without DMA (no burst mode)
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* Args: unlock_pup Bit array of the unlock pups
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* new_locked_pup Output bit array of the pups with failed compare
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* pattern Pattern to compare
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* pattern_len Length of pattern (in bytes)
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* sdram_offset offset address to the SDRAM
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* write write to the SDRAM before read
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* mask compare pattern with mask;
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* auiMaskPatter Mask to compare pattern
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*
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* Notes:
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 pattern_len, u32 sdram_offset,
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int write, int mask, u32 *mask_pattern)
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{
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u32 uj, uk, pup_groups;
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u32 *sdram_addr; /* used to read from SDRAM */
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sdram_addr = (u32 *)sdram_offset;
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if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
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pup_groups = 2;
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else
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pup_groups = 1;
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/* Check if need to write before read */
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if (write == 1) {
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for (uk = 0; uk < pattern_len; uk++) {
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*sdram_addr = pattern[uk];
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sdram_addr++;
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}
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}
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sdram_addr = (u32 *)sdram_offset;
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for (uk = 0; uk < pattern_len; uk++) {
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sdram_data[uk] = *sdram_addr;
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sdram_addr++;
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}
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/* Compare read result to write */
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for (uj = 0; uj < pattern_len; uj++) {
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if (dram_info->ddr_width > 16) {
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compare_pattern_v1(uj, new_locked_pup, pattern,
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pup_groups, 0);
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} else {
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compare_pattern_v2(uj, new_locked_pup, pattern);
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}
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}
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return MV_OK;
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}
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/*
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* Name: ddr3_dram_sram_burst
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* Desc: Read from the SDRAM in burst of 64 bytes
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* Args: src
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* dst
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* Notes: Using the XOR mechanism
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* Returns: MV_OK if success, other error code if fail.
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*/
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int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len)
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{
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u32 chan, byte_count, cs_num, byte;
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struct xor_channel_t channel;
|
|
|
|
chan = 0;
|
|
byte_count = len * 4;
|
|
|
|
/* Wait for previous transfer completion */
|
|
while (mv_xor_state_get(chan) != MV_IDLE)
|
|
;
|
|
|
|
/* Build the channel descriptor */
|
|
channel.desc = &dma_desc;
|
|
|
|
/* Enable Address Override and set correct src and dst */
|
|
if (src < SRAM_BASE) {
|
|
/* src is DRAM CS, dst is SRAM */
|
|
cs_num = (src / (1 + SDRAM_CS_SIZE));
|
|
reg_write(XOR_ADDR_OVRD_REG(0, 0),
|
|
((cs_num << 1) | (1 << 0)));
|
|
channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE));
|
|
channel.desc->dst_addr = dst;
|
|
} else {
|
|
/* src is SRAM, dst is DRAM CS */
|
|
cs_num = (dst / (1 + SDRAM_CS_SIZE));
|
|
reg_write(XOR_ADDR_OVRD_REG(0, 0),
|
|
((cs_num << 25) | (1 << 24)));
|
|
channel.desc->src_addr0 = (src);
|
|
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
|
|
channel.desc->src_addr0 = src;
|
|
channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE));
|
|
}
|
|
|
|
channel.desc->src_addr1 = 0;
|
|
channel.desc->byte_cnt = byte_count;
|
|
channel.desc->next_desc_ptr = 0;
|
|
channel.desc->status = 1 << 31;
|
|
channel.desc->desc_cmd = 0x0;
|
|
channel.desc_phys_addr = (unsigned long)&dma_desc;
|
|
|
|
ddr3_flush_l1_line((u32)&dma_desc);
|
|
|
|
/* Issue the transfer */
|
|
if (mv_xor_transfer(chan, MV_DMA, channel.desc_phys_addr) != MV_OK)
|
|
return MV_FAIL;
|
|
|
|
/* Wait for completion */
|
|
xor_waiton_eng(chan);
|
|
|
|
if (dst > SRAM_BASE) {
|
|
for (byte = 0; byte < byte_count; byte += 0x20)
|
|
cache_inv(dst + byte);
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
/*
|
|
* Name: ddr3_flush_l1_line
|
|
* Desc:
|
|
* Args:
|
|
* Notes:
|
|
* Returns: MV_OK if success, other error code if fail.
|
|
*/
|
|
static void ddr3_flush_l1_line(u32 line)
|
|
{
|
|
u32 reg;
|
|
|
|
#if defined(MV88F672X)
|
|
reg = 1;
|
|
#else
|
|
reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) &
|
|
(1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
|
|
#ifdef MV88F67XX
|
|
reg = ~reg & (1 << REG_SAMPLE_RESET_CPU_ARCH_OFFS);
|
|
#endif
|
|
#endif
|
|
|
|
if (reg) {
|
|
/* V7 Arch mode */
|
|
flush_l1_v7(line);
|
|
flush_l1_v7(line + CACHE_LINE_SIZE);
|
|
} else {
|
|
/* V6 Arch mode */
|
|
flush_l1_v6(line);
|
|
flush_l1_v6(line + CACHE_LINE_SIZE);
|
|
}
|
|
}
|
|
|
|
int ddr3_dram_sram_read(u32 src, u32 dst, u32 len)
|
|
{
|
|
u32 ui;
|
|
u32 *dst_ptr, *src_ptr;
|
|
|
|
dst_ptr = (u32 *)dst;
|
|
src_ptr = (u32 *)src;
|
|
|
|
for (ui = 0; ui < len; ui++) {
|
|
*dst_ptr = *src_ptr;
|
|
dst_ptr++;
|
|
src_ptr++;
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
|
|
u32 *new_locked_pup, u32 *pattern,
|
|
u32 pattern_len, u32 sdram_offset, int write,
|
|
int mask, u32 *mask_pattern,
|
|
int special_compare)
|
|
{
|
|
u32 uj, pup_groups;
|
|
|
|
if (dram_info->num_of_std_pups == PUP_NUM_64BIT)
|
|
pup_groups = 2;
|
|
else
|
|
pup_groups = 1;
|
|
|
|
ddr3_reset_phy_read_fifo();
|
|
|
|
/* Check if need to write to sdram before read */
|
|
if (write == 1)
|
|
ddr3_dram_sram_burst((u32)pattern, sdram_offset, pattern_len);
|
|
|
|
ddr3_dram_sram_burst(sdram_offset, (u32)sdram_data, pattern_len);
|
|
|
|
/* Compare read result to write */
|
|
for (uj = 0; uj < pattern_len; uj++) {
|
|
if (special_compare && special_compare_pattern(uj))
|
|
continue;
|
|
|
|
if (dram_info->ddr_width > 16) {
|
|
compare_pattern_v1(uj, new_locked_pup, pattern,
|
|
pup_groups, 1);
|
|
} else {
|
|
compare_pattern_v2(uj, new_locked_pup, pattern);
|
|
}
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
void ddr3_reset_phy_read_fifo(void)
|
|
{
|
|
u32 reg;
|
|
|
|
/* reset read FIFO */
|
|
reg = reg_read(REG_DRAM_TRAINING_ADDR);
|
|
/* Start Auto Read Leveling procedure */
|
|
reg |= (1 << REG_DRAM_TRAINING_RL_OFFS);
|
|
|
|
/* 0x15B0 - Training Register */
|
|
reg_write(REG_DRAM_TRAINING_ADDR, reg);
|
|
|
|
reg = reg_read(REG_DRAM_TRAINING_2_ADDR);
|
|
reg |= ((1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS) +
|
|
(1 << REG_DRAM_TRAINING_2_SW_OVRD_OFFS));
|
|
|
|
/* [0] = 1 - Enable SW override, [4] = 1 - FIFO reset */
|
|
/* 0x15B8 - Training SW 2 Register */
|
|
reg_write(REG_DRAM_TRAINING_2_ADDR, reg);
|
|
|
|
do {
|
|
reg = reg_read(REG_DRAM_TRAINING_2_ADDR) &
|
|
(1 << REG_DRAM_TRAINING_2_FIFO_RST_OFFS);
|
|
} while (reg); /* Wait for '0' */
|
|
|
|
reg = reg_read(REG_DRAM_TRAINING_ADDR);
|
|
|
|
/* Clear Auto Read Leveling procedure */
|
|
reg &= ~(1 << REG_DRAM_TRAINING_RL_OFFS);
|
|
|
|
/* 0x15B0 - Training Register */
|
|
reg_write(REG_DRAM_TRAINING_ADDR, reg);
|
|
}
|