fab70acf83
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test Signed-off-by: Ken Lin <yungching0725@gmail.com> Acked-by: Akshay Bhat <akshay.bhat@timesys.com> |
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| .. | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| clocks.cfg | ||
| ddr-setup.cfg | ||
| dms-ba16.c | ||
| dms-ba16_1g.cfg | ||
| dms-ba16_2g.cfg | ||
| micron-1g.cfg | ||
| samsung-2g.cfg | ||