155 lines
2.6 KiB
C
155 lines
2.6 KiB
C
/*
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* (C) Copyright 2011
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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enum {
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UNITTYPE_CCX16 = 1,
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UNITTYPE_CCIP216 = 2,
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};
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enum {
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HWVER_300 = 3,
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};
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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int misc_init_r(void)
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{
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/*
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* Note: DTT has been removed. Please use UCLASS_THERMAL.
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*
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* startup fans
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*
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* dtt_init();
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*/
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: CATCenter Neo");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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static void print_fpga_info(void)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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int fpga_state = get_fpga_state(0);
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_channels;
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puts("FPGA: ");
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if (fpga_state & FPGA_STATE_DONE_FAILED) {
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printf(" done timed out\n");
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return;
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}
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if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
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printf(" refelectione test failed\n");
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return;
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}
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FPGA_GET_REG(0, versions, &versions);
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FPGA_GET_REG(0, fpga_version, &fpga_version);
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_channels = fpga_features & 0x007f;
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switch (unit_type) {
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case UNITTYPE_CCX16:
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printf("CCX-Switch");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_300:
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printf(" HW-Ver 3.00-3.12\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %d channel(s)\n", feature_channels);
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}
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int last_stage_init(void)
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{
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print_fpga_info();
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return 0;
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}
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void gd405ep_init(void)
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{
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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}
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void gd405ep_setup_hw(void)
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{
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/*
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* set "startup-finished"-gpios
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*/
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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}
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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/*
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* Neo hardware has no FPGA-DONE GPIO
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*/
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return 1;
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}
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