80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
/*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx_config.h>
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/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
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struct ppc4xx_config ppc4xx_config_val[] = {
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{
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"333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
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{
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
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{
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
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{
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0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
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{
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
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{
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
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{
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
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{
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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{
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"600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
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{
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
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0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
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}
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},
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{
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"666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
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{
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
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}
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},
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};
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
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