150 lines
4.8 KiB
C
150 lines
4.8 KiB
C
/*
|
|
* (C) Copyright 2016 Savoir-faire Linux Inc.
|
|
*
|
|
* Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
|
|
*
|
|
* Based on work from TS7680 code by:
|
|
* Kris Bahnsen <kris@embeddedarm.com>
|
|
* Mark Featherston <mark@embeddedarm.com>
|
|
* https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
|
|
*
|
|
* Derived from MX28EVK code by
|
|
* Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <config.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/iomux-mx28.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
|
|
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
|
|
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
|
|
|
|
const iomux_cfg_t iomux_setup[] = {
|
|
/* DUART */
|
|
MX28_PAD_PWM0__DUART_RX,
|
|
MX28_PAD_PWM1__DUART_TX,
|
|
|
|
/* MMC0 */
|
|
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
|
|
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
|
|
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
|
|
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
|
|
MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
|
|
MX28_PAD_SSP0_SCK__SSP0_SCK |
|
|
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
|
|
|
/* MMC0 slot power enable */
|
|
MX28_PAD_PWM3__GPIO_3_28 |
|
|
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
|
|
|
|
/* EMI */
|
|
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
|
|
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
|
|
|
|
/* I2C */
|
|
MX28_PAD_I2C0_SCL__I2C0_SCL,
|
|
MX28_PAD_I2C0_SDA__I2C0_SDA,
|
|
|
|
};
|
|
|
|
#define HW_DRAM_CTL29 (0x74 >> 2)
|
|
#define CS_MAP 0xf
|
|
#define COLUMN_SIZE 0x2
|
|
#define ADDR_PINS 0x1
|
|
#define APREBIT 0xa
|
|
|
|
#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
|
|
ADDR_PINS << 8 | APREBIT)
|
|
|
|
#define HW_DRAM_CTL39 (0x9c >> 2)
|
|
#define TFAW 0xb
|
|
#define TDLL 0xc8
|
|
|
|
#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL)
|
|
|
|
#define HW_DRAM_CTL41 (0xa4 >> 2)
|
|
#define TPDEX 0x2
|
|
#define TRCD_INT 0x4
|
|
#define TRC 0xd
|
|
|
|
#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC)
|
|
|
|
#define HW_DRAM_CTL42 (0xa8 >> 2)
|
|
#define TRAS_MAX 0x36a6
|
|
#define TRAS_MIN 0xa
|
|
|
|
#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN)
|
|
|
|
#define HW_DRAM_CTL43 (0xac >> 2)
|
|
#define TRP 0x4
|
|
#define TRFC 0x27
|
|
#define TREF 0x2a0
|
|
|
|
#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
|
|
|
|
void mxs_adjust_memory_params(uint32_t *dram_vals)
|
|
{
|
|
dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
|
|
dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
|
|
dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
|
|
dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
|
|
dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
|
|
}
|
|
|
|
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
|
|
{
|
|
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
|
|
}
|