288 lines
8.2 KiB
C
288 lines
8.2 KiB
C
/*
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* (C) Copyright 2003-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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#define CONFIG_CM5200 1 /* ... on CM5200 platform */
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#define CONFIG_SYS_TEXT_BASE 0xfc000000
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Supported commands
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*/
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_REGINFO
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x00
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#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
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/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
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/*
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* POST support
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*/
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU)
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#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
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/* List of I2C addresses to be verified by POST */
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#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
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CONFIG_SYS_I2C_IO, \
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CONFIG_SYS_I2C_EEPROM}
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/* display image timestamps */
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#define CONFIG_TIMESTAMP 1
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/*
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* Autobooting
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*/
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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/*
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* Default environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"netmask=255.255.0.0\0" \
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"ipaddr=192.168.160.33\0" \
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"serverip=192.168.1.1\0" \
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"gatewayip=192.168.1.1\0" \
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"console=ttyPSC0\0" \
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"u-boot_addr=100000\0" \
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"kernel_addr=200000\0" \
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"kernel_addr_flash=fc0c0000\0" \
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"fdt_addr=400000\0" \
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"fdt_addr_flash=fc0a0000\0" \
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"ramdisk_addr=500000\0" \
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"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
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"u-boot=/tftpboot/cm5200/u-boot.bin\0" \
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"bootfile_fdt=/tftpboot/cm5200/uImage\0" \
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"fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
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"load=tftp ${u-boot_addr} ${u-boot}\0" \
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"update=prot off fc000000 +${filesize}; " \
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"era fc000000 +${filesize}; " \
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"cp.b ${u-boot_addr} fc000000 ${filesize}; " \
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"prot on fc000000 +${filesize}\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
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"addcons=setenv bootargs ${bootargs} " \
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"console=${console},${baudrate}\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:${hostname}:${netdev}:off panic=1\0" \
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"flash_flash=run flashargs addinit addip addcons;" \
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"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
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"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
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"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
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"addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_flash"
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/*
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* Low level configuration
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*/
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/*
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* Clock configuration
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*/
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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#define CONFIG_SYS_LOWBOOT 1
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/* Use ON-Chip SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#ifdef CONFIG_POST
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/* preserve space for the post_word at end of on-chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
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#else
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#endif
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_BOARD_TYPES 1 /* we use board_type */
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_BASE 0xfc000000
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/* we need these despite using CFI */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
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#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT 1
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#undef CONFIG_SYS_LOWBOOT
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#endif
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/*
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* Chip selects configuration
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*/
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/* Boot Chipselect */
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
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/* use board_early_init_r to enable flash write in CS_BOOT */
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#define CONFIG_BOARD_EARLY_INIT_R
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/* Flash memory addressing */
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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/* No burst, dead cycle = 1 for CS0 (Flash) */
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x00000001
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/*
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* SDRAM configuration
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* settings for k4s561632E-xx75, assuming XLB = 132 MHz
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*/
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#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
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#define SDRAM_CONTROL 0x514F0000
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#define SDRAM_CONFIG1 0xE2333900
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#define SDRAM_CONFIG2 0x8EE70000
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/*
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* MTD configuration
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*/
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#define CONFIG_CMD_MTDPARTS 1
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=cm5200-0"
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#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
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"384k(uboot),128k(env)," \
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"128k(redund_env),128k(dtb)," \
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"2m(kernel),27904k(rootfs)," \
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"-(config)"
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
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/*
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* USB configuration
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*/
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#define CONFIG_USB_OHCI 1
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
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/* Partitions (for USB) */
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/*
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* Invoke our last_stage_init function - needed by fwupdate
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*/
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#define CONFIG_LAST_STAGE_INIT 1
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Configuration of redundant environment */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* Pin multiplexing configuration
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*/
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/*
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* CS1/GPIO_WKUP_6: GPIO (default)
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* ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
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* IRDA/PSC6: UART
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* Ether: Ethernet 100Mbit with MD
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* PCI_DIS: PCI controller disabled
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* USB: USB
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* PSC3: SPI with UART3
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* PSC2: UART
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* PSC1: UART
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_ALT_MEMTEST 1
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Flat Device Tree support
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*/
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
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#endif /* __CONFIG_H */
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