arm: dts: ti: k3-j721s2: Add ESM instances
Patch adds the ESM instances for j721s2. It has 3 instances. One in the main domain and two in the mcu-wakeup domian. Signed-off-by: Keerthy <j-keerthy@ti.com>
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				|  | @ -1184,4 +1184,11 @@ | ||||||
| 		resets = <&k3_reset 11 1>; | 		resets = <&k3_reset 11 1>; | ||||||
| 		firmware-name = "j721s2-c71_1-fw"; | 		firmware-name = "j721s2-c71_1-fw"; | ||||||
| 	}; | 	}; | ||||||
|  | 
 | ||||||
|  | 	main_esm: esm@700000 { | ||||||
|  | 		compatible = "ti,j721e-esm"; | ||||||
|  | 		reg = <0x00 0x700000 0x00 0x1000>; | ||||||
|  | 		ti,esm-pins = <688>, <689>; | ||||||
|  | 		bootph-pre-ram; | ||||||
|  | 	}; | ||||||
| }; | }; | ||||||
|  |  | ||||||
|  | @ -380,4 +380,18 @@ | ||||||
| 			#size-cells = <0>; | 			#size-cells = <0>; | ||||||
| 		}; | 		}; | ||||||
| 	}; | 	}; | ||||||
|  | 
 | ||||||
|  | 	mcu_esm: esm@40800000 { | ||||||
|  | 		compatible = "ti,j721e-esm"; | ||||||
|  | 		reg = <0x00 0x40800000 0x00 0x1000>; | ||||||
|  | 		ti,esm-pins = <95>; | ||||||
|  | 		bootph-pre-ram; | ||||||
|  | 	}; | ||||||
|  | 
 | ||||||
|  | 	wkup_esm: esm@42080000 { | ||||||
|  | 		compatible = "ti,j721e-esm"; | ||||||
|  | 		reg = <0x00 0x42080000 0x00 0x1000>; | ||||||
|  | 		ti,esm-pins = <63>; | ||||||
|  | 		bootph-pre-ram; | ||||||
|  | 	}; | ||||||
| }; | }; | ||||||
|  |  | ||||||
|  | @ -114,6 +114,7 @@ | ||||||
| 		#size-cells = <2>; | 		#size-cells = <2>; | ||||||
| 		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ | 		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ | ||||||
| 			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ | 			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ | ||||||
|  | 			 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ | ||||||
| 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ | 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ | ||||||
| 			 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ | 			 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ | ||||||
| 			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ | 			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ | ||||||
|  |  | ||||||
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