arm: dts: k3-j721s2: Add OSPI1 description necessary for QSPI boot
Add OSPI1 description and pinmux node in j721s2-r5 dts which is necessary for enabling QSPI boot support. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
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@ -146,6 +146,20 @@
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J721S2_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
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>;
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};
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mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
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pinctrl-single,pins = <
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J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
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J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
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J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
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J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
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J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
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J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
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J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
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J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
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J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
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>;
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};
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};
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&sms {
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@ -232,4 +246,27 @@
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#size-cells = <1>;
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};
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};
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&ospi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
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reg = <0x0 0x47050000 0x0 0x100>,
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<0x0 0x58000000 0x0 0x8000000>;
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flash@0{
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <40000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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#include "k3-j721s2-common-proc-board-u-boot.dtsi"
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