MLK-18591-10 android: iot: Update imx7d pico board support
Update imx7d pico board support for android things and trusty OS, porting from v2017.03 Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
parent
90832f970e
commit
02ad0349e4
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@ -18,7 +18,11 @@ IMAGE_VERSION 2
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BOOT_FROM sd
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/* Secure boot support */
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/technexion/pico-imx7d/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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@ -96,3 +100,5 @@ DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -0,0 +1,156 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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* 2015-2016 Toradex AG
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/technexion/pico-imx7d/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* IOMUXC_GPR_GPR1 */
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DATA 4 0x30340004 0x4F400005
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/* DDR3L */
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/* assuming MEMC_FREQ_RATIO = 2 */
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/* SRC_DDRC_RCR */
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DATA 4 0x30391000 0x00000002
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/* DDRC_MSTR */
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DATA 4 0x307a0000 0x01040001
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/* DDRC_RFSHTMG */
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DATA 4 0x307a0064 0x00400046
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/* DDRC_MP_PCTRL_0 */
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DATA 4 0x307a0490 0x00000001
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/* DDRC_INIT0 */
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DATA 4 0x307a00d0 0x00020083
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/* DDRC_INIT1 */
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DATA 4 0x307a00d4 0x00690000
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/* DDRC_INIT3 MR0/MR1 */
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DATA 4 0x307a00dc 0x09300004
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/* DDRC_INIT4 MR2/MR3 */
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DATA 4 0x307a00e0 0x04080000
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/* DDRC_INIT5 */
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DATA 4 0x307a00e4 0x00100004
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/* DDRC_RANKCTL */
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DATA 4 0x307a00f4 0x0000033f
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/* DDRC_DRAMTMG0 */
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DATA 4 0x307a0100 0x09081109
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/* DDRC_DRAMTMG1 */
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DATA 4 0x307a0104 0x0007020D
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/* DDRC_DRAMTMG2 */
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DATA 4 0x307a0108 0x03040407
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/* DDRC_DRAMTMG3 */
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DATA 4 0x307a010c 0x00002006
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/* DDRC_DRAMTMG4 */
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DATA 4 0x307a0110 0x04020205
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/* DDRC_DRAMTMG5 */
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DATA 4 0x307a0114 0x03030202
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/* DDRC_DRAMTMG8 */
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DATA 4 0x307a0120 0x00000803
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/* DDRC_ZQCTL0 */
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DATA 4 0x307a0180 0x00800020
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/* DDRC_DFITMG0 */
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DATA 4 0x307a0190 0x02098204
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/* DDRC_DFITMG1 */
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DATA 4 0x307a0194 0x00030303
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/* DDRC_DFIUPD0 */
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DATA 4 0x307a01a0 0x80400003
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/* DDRC_DFIUPD1 */
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DATA 4 0x307a01a4 0x00100020
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/* DDRC_DFIUPD2 */
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DATA 4 0x307a01a8 0x80100004
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/* DDRC_ADDRMAP0 */
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DATA 4 0x307a0200 0x00000015
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/* DDRC_ADDRMAP1 */
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DATA 4 0x307a0204 0x00161616
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/* DDRC_ADDRMAP4 */
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DATA 4 0x307A0210 0x00000F0F
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/* DDRC_ADDRMAP5 */
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DATA 4 0x307a0214 0x04040404
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/* DDRC_ADDRMAP6 */
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DATA 4 0x307a0218 0x0F0F0404
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/* DDRC_ODTCFG */
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DATA 4 0x307a0240 0x06000604
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/* DDRC_ODTMAP */
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DATA 4 0x307a0244 0x00000001
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/* SRC_DDRC_RCR */
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DATA 4 0x30391000 0x00000000
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/* DDR_PHY_PHY_CON0 */
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DATA 4 0x30790000 0x17420f40
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/* DDR_PHY_PHY_CON1 */
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DATA 4 0x30790004 0x10210100
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/* DDR_PHY_PHY_CON4 */
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DATA 4 0x30790010 0x00060807
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/* DDR_PHY_MDLL_CON0 */
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DATA 4 0x307900b0 0x1010007e
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/* DDR_PHY_DRVDS_CON0 */
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DATA 4 0x3079009c 0x00000d6e
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/* DDR_PHY_OFFSET_RD_CON0 */
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DATA 4 0x30790020 0x08080808
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/* DDR_PHY_OFFSET_WR_CON0 */
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DATA 4 0x30790030 0x08080808
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/* DDR_PHY_CMD_SDLL_CON0 */
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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/* DDR_PHY_ZQ_CON0 */
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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/* DDR_PHY_ZQ_CON1 */
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CHECK_BITS_SET 4 0x307900c4 0x1
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/* DDR_PHY_ZQ_CON0 */
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e407304
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/* CCM_CCGRn */
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DATA 4 0x30384130 0x00000000
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/* IOMUXC_GPR_GPR8 */
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DATA 4 0x30340020 0x00000178
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/* CCM_CCGRn */
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DATA 4 0x30384130 0x00000002
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/* DDR_PHY_LP_CON0 */
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DATA 4 0x30790018 0x0000000f
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/* DDRC_STAT */
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -11,6 +11,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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@ -23,6 +24,21 @@
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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#if defined(CONFIG_MXC_EPDC)
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#include <lcd.h>
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#include <mxc_epdc_fb.h>
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#endif
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#ifdef CONFIG_VIDEO_MXS
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#include <linux/fb.h>
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#include <mxsfb.h>
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#endif
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#ifdef CONFIG_FSL_FASTBOOT
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#include <fsl_fastboot.h>
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#ifdef CONFIG_ANDROID_RECOVERY
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#include <recovery.h>
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#endif
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#endif /*CONFIG_FSL_FASTBOOT*/
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DECLARE_GLOBAL_DATA_PTR;
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@ -40,8 +56,39 @@ DECLARE_GLOBAL_DATA_PTR;
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_49OHM)
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1*/
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX7D_PAD_UART1_RX_DATA__I2C1_SCL | PC,
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.gpio_mode = MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 | PC,
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.gp = IMX_GPIO_NR(4, 0),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_UART1_TX_DATA__I2C1_SDA | PC,
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.gpio_mode = MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 | PC,
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.gp = IMX_GPIO_NR(4, 1),
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},
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};
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/* I2C2 */
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static struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX7D_PAD_UART2_RX_DATA__I2C2_SCL | PC,
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.gpio_mode = MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 | PC,
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.gp = IMX_GPIO_NR(4, 2),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_UART2_TX_DATA__I2C2_SDA | PC,
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.gpio_mode = MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 | PC,
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.gp = IMX_GPIO_NR(4, 3),
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},
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};
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/* I2C4 for PMIC */
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static struct i2c_pads_info i2c_pad_info4 = {
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.scl = {
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@ -59,7 +106,11 @@ static struct i2c_pads_info i2c_pad_info4 = {
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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#ifdef CONFIG_IMX_TRUSTY_OS
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gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024) - TRUSTY_OS_RAM_SIZE;
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#else
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gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
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#endif
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return 0;
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}
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@ -103,7 +154,7 @@ int power_init_board(void)
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/* decrease SW1B normal voltage to 0.975V */
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
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reg &= ~0x1f;
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reg |= PFUZE3000_SW1AB_SETP(975);
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reg |= PFUZE3000_SW1AB_SETP(9750);
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
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return 0;
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@ -119,6 +170,32 @@ static iomux_v3_cfg_t const uart5_pads[] = {
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_RESET_B__SD1_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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/* SD */
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#ifdef PICO_SD
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#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 9)
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__GPIO6_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#else
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/* EMMC */
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#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
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static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -132,11 +209,131 @@ static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
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MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* LCD_VDD_EN */
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};
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static iomux_v3_cfg_t const pwm_pads[] = {
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/* Use GPIO for Brightness adjustment, duty cycle = period */
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MX7D_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* LCD_BLT_CTRL */
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};
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struct lcd_panel_info_t {
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unsigned int lcdif_base_addr;
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int depth;
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void (*enable)(struct lcd_panel_info_t const *dev);
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struct fb_videomode mode;
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};
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void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
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imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
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/* Reset LCD */
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gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
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udelay(500);
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gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
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/* Set Brightness to high */
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gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
|
||||
/* Set LCD enable to high */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 6) , 1);
|
||||
}
|
||||
|
||||
static struct lcd_panel_info_t const displays[] = {{
|
||||
.lcdif_base_addr = ELCDIF1_IPS_BASE_ADDR,
|
||||
.depth = 24,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "EJ050NA",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
|
||||
int board_video_skip(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
char const *panel = env_get("panel");
|
||||
if (!panel) {
|
||||
panel = displays[0].mode.name;
|
||||
printf("No panel detected: default to %s\n", panel);
|
||||
i = 0;
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) {
|
||||
if (!strcmp(panel, displays[i].mode.name))
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i < ARRAY_SIZE(displays)) {
|
||||
ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
|
||||
displays[i].lcdif_base_addr);
|
||||
if (!ret) {
|
||||
if (displays[i].enable)
|
||||
displays[i].enable(displays+i);
|
||||
printf("Display: %s (%ux%u)\n",
|
||||
displays[i].mode.name,
|
||||
displays[i].mode.xres,
|
||||
displays[i].mode.yres);
|
||||
} else
|
||||
printf("LCD %s cannot be configured: %d\n",
|
||||
displays[i].mode.name, ret);
|
||||
} else {
|
||||
printf("unsupported panel %s\n", panel);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_SD2_CD_B__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_SD2_WP__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
|
|
@ -187,10 +384,16 @@ static int setup_fec(void)
|
|||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* enable rgmii rxc skew and phy mode select to RGMII copper */
|
||||
/*phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);*/
|
||||
|
||||
unsigned short val;
|
||||
|
||||
/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
/* phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
||||
|
||||
|
|
@ -198,7 +401,7 @@ int board_phy_config(struct phy_device *phydev)
|
|||
val &= 0xffe7;
|
||||
val |= 0x18;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
|
||||
|
||||
*/
|
||||
/* introduce tx clock delay */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
|
||||
|
|
@ -207,46 +410,153 @@ int board_phy_config(struct phy_device *phydev)
|
|||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static iomux_v3_cfg_t const bcm4339_pads[] = {
|
||||
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), //wifi reset
|
||||
MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), //bt reset
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const ccm_clko_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO03__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX7D_PAD_GPIO1_IO02__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
|
||||
}
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
||||
{USDHC1_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
if (2 == devno)
|
||||
devno--;
|
||||
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
if (1 == dev_no)
|
||||
dev_no++;
|
||||
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
/* Assume uSDHC3 emmc is always present */
|
||||
return 1;
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO); /* Assume uSDHC1 sd is always present */
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO); /* Assume uSDHC3 emmc is always present */
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
int i, ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc2 USDHC3 (eMMC)
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
|
||||
gpio_request(USDHC3_CD_GPIO, "usdhc3_cd");
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int check_mmc_autodetect(void)
|
||||
{
|
||||
char *autodetect_str = env_get("mmcautodetect");
|
||||
|
||||
if ((autodetect_str != NULL) &&
|
||||
(strcmp(autodetect_str, "yes") == 0)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_late_mmc_init(void)
|
||||
{
|
||||
char cmd[32];
|
||||
char mmcblk[32];
|
||||
u32 dev_no = mmc_get_env_dev();
|
||||
|
||||
if (!check_mmc_autodetect())
|
||||
return;
|
||||
|
||||
env_set_ulong("mmcdev", dev_no);
|
||||
|
||||
/* Set mmcblk env */
|
||||
sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
|
||||
mmc_map_to_kernel_blk(dev_no));
|
||||
env_set("mmcroot", mmcblk);
|
||||
|
||||
sprintf(cmd, "mmc dev %d", dev_no);
|
||||
run_command(cmd, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define BT_RST_GPIO IMX_GPIO_NR(6, 16)
|
||||
#define WIFI_RST_GPIO IMX_GPIO_NR(6, 17)
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
|
|
@ -256,34 +566,96 @@ int board_init(void)
|
|||
setup_fec();
|
||||
#endif
|
||||
|
||||
//pico-imx7 custom initialize
|
||||
imx_iomux_v3_setup_multiple_pads(bcm4339_pads, ARRAY_SIZE(bcm4339_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(ccm_clko_pads, ARRAY_SIZE(ccm_clko_pads));
|
||||
|
||||
gpio_direction_output(BT_RST_GPIO, 1);
|
||||
udelay(500);
|
||||
gpio_direction_output(WIFI_RST_GPIO, 1);
|
||||
udelay(500);
|
||||
clock_set_src(IPP_DO_CLKO2,OSC_32K_CLK);
|
||||
udelay(500);
|
||||
clock_set_src(IPP_DO_CLKO1,OSC_24M_CLK);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
|
||||
{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
|
||||
/* TODO: Nand */
|
||||
/*{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},*/
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_init();
|
||||
#endif
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
/*
|
||||
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
||||
* since we use PMIC_PWRON to reset the board.
|
||||
*/
|
||||
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: i.MX7D PICOSOM\n");
|
||||
char *mode;
|
||||
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
|
||||
mode = "secure";
|
||||
else
|
||||
mode = "non-secure";
|
||||
|
||||
printf("Board: i.MX7D PICOSOM in %s mode\n", mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
return USB_INIT_DEVICE;
|
||||
switch (port) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
|
||||
ARRAY_SIZE(usb_otg1_pads));
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("MXC USB port %d not yet supported\n", port);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_FASTBOOT
|
||||
#ifdef CONFIG_ANDROID_RECOVERY
|
||||
int is_recovery_key_pressing(void)
|
||||
{
|
||||
/* No key defined for this board */
|
||||
return 0;
|
||||
}
|
||||
#endif /*CONFIG_ANDROID_RECOVERY*/
|
||||
#endif /*CONFIG_FSL_FASTBOOT*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx7d_ddrphy_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne NO_DELAY
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x00000dee
|
||||
str r1, [r0, #0x9c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x40401818
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x00000040
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x40404040
|
||||
str r1, [r0, #0x6c]
|
||||
b TUNE_END
|
||||
|
||||
NO_DELAY:
|
||||
/*TO 1.0*/
|
||||
ldr r1, =0x00000b24
|
||||
str r1, [r0, #0x9c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_ddr_freq_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne FREQ_DEFAULT_533
|
||||
|
||||
/* Change to 400Mhz for TO1.1 */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00703021
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x90
|
||||
ldr r2, =0x0
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00603021
|
||||
str r2, [r0, r1]
|
||||
|
||||
ldr r3, =0x80000000
|
||||
wait_lock:
|
||||
ldr r2, [r0, r1]
|
||||
and r2, r3
|
||||
cmp r2, r3
|
||||
bne wait_lock
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x9880
|
||||
ldr r2, =0x1
|
||||
str r2, [r0, r1]
|
||||
|
||||
FREQ_DEFAULT_533:
|
||||
.endm
|
||||
|
||||
.macro imx7d_sabresd_ddr_setting
|
||||
imx7d_ddr_freq_setting
|
||||
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =(0x1 << 30)
|
||||
str r1, [r0, #0x388]
|
||||
str r1, [r0, #0x384]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x01040001
|
||||
str r1, [r0]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
ldr r1, =0x00400046
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00020001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00690000
|
||||
str r1, [r0, #0xd4]
|
||||
ldr r1, =0x09300004
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x04080000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00100004
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x09081109
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x0007020d
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x03040407
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00002006
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x04020205
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x03030202
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x00000803
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00800020
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x02000100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098204
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00030303
|
||||
str r1, [r0, #0x194]
|
||||
|
||||
ldr r1, =0x00000016
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00080808
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f0f
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x07070707
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f070707
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000604
|
||||
str r1, [r0, #0x240]
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17420f40
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00060807
|
||||
str r1, [r0, #0x10]
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
imx7d_ddrphy_latency_setting
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x01000010
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x178
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7_clock_gating
|
||||
.endm
|
||||
|
||||
.macro imx7_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx7_ddr_setting
|
||||
imx7d_sabresd_ddr_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx7_plugin.S>
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX7=y
|
||||
CONFIG_IMX_TRUSTY_OS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_TARGET_PICO_IMX7D=y
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
CONFIG_IMX_RDC=y
|
||||
CONFIG_BOOTDELAY=-2
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage_512mb.cfg,ANDROID_THINGS_SUPPORT,DDR_MB=512,ARMV7_NONSEC"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_AVB_ATX=y
|
||||
|
|
@ -2,8 +2,17 @@ CONFIG_ARM=y
|
|||
CONFIG_ARCH_MX7=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_TARGET_PICO_IMX7D=y
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
CONFIG_IMX_RDC=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=-2
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage_512mb.cfg,ANDROID_THINGS_SUPPORT,DDR_MB=512"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
|
|
@ -14,23 +23,16 @@ CONFIG_CMD_I2C=y
|
|||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_MXC_USB_OTG_HACTIVE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_AVB_ATX=y
|
||||
|
|
|
|||
|
|
@ -11,13 +11,10 @@
|
|||
|
||||
#include "mx7_common.h"
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
|
|
@ -25,40 +22,106 @@
|
|||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_BROADCOM
|
||||
|
||||
/* ENET1 */
|
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET2_IPS_BASE_ADDR
|
||||
|
||||
/* MMC Config */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 /* Set to QSPI1 A flash at default */
|
||||
#ifdef CONFIG_CMD_BOOTAUX
|
||||
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
|
||||
"update_m4_from_sd=" \
|
||||
"if sf probe 0:0; then " \
|
||||
"if run loadm4image; then " \
|
||||
"setexpr fw_sz ${filesize} + 0xffff; " \
|
||||
"setexpr fw_sz ${fw_sz} / 0x10000; " \
|
||||
"setexpr fw_sz ${fw_sz} * 0x10000; " \
|
||||
"sf erase 0x0 ${fw_sz}; " \
|
||||
"sf write ${loadaddr} 0x0 ${filesize}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#if defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"panel=EJ050NA\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc4\0" \
|
||||
"bootargs=console=ttymxc4,115200 ubi.mtd=3 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
UPDATE_M4_ENV \
|
||||
"panel=EJ050NA\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc4\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7d-pico.dtb\0" \
|
||||
"fdt_file=imx7d-pico_dwarf.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"finduuid=part uuid mmc 0:2 uuid\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"root=${mmcroot} 2\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
|
|
@ -71,19 +134,33 @@
|
|||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
|
||||
|
|
@ -122,13 +199,50 @@
|
|||
/* FLASH and environment organization */
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#define CONFIG_ENV_OFFSET (13 * SZ_64K)
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#endif
|
||||
|
||||
/* #define CONFIG_SPLASH_SCREEN*/
|
||||
/* #define CONFIG_MXC_EPDC*/
|
||||
|
||||
/*
|
||||
* SPLASH SCREEN Configs
|
||||
*/
|
||||
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
|
||||
/*
|
||||
* Framebuffer and LCD
|
||||
*/
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
#undef LCD_TEST_PATTERN
|
||||
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
|
||||
#define LCD_BPP LCD_MONOCHROME
|
||||
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
|
||||
|
||||
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_USB_EHCI_MX7
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
|
@ -136,4 +250,15 @@
|
|||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI)
|
||||
#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
|
||||
#include "pico-imx7dandroidthings.h"
|
||||
#endif
|
||||
|
||||
#define PRODUCT_NAME "imx7d"
|
||||
#define VARIANT_NAME "imx7d_pico"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __PICO_IMX7DANDROIDTHINGS_H
|
||||
#define __PICO_IMX7DANDROIDTHINGS_H
|
||||
|
||||
#define TRUSTY_OS_ENTRY 0x9e000000
|
||||
#define TRUSTY_OS_RAM_SIZE 0x2000000
|
||||
#define TEE_HWPARTITION_ID 2
|
||||
#define TRUSTY_OS_MMC_BLKS 0xFFF
|
||||
|
||||
#ifdef CONFIG_AVB_ATX
|
||||
#define PERMANENT_ATTRIBUTE_HASH_OFFSET 0
|
||||
#endif
|
||||
|
||||
#define AVB_RPMB
|
||||
#ifdef AVB_RPMB
|
||||
#define KEYSLOT_BLKS 0xFFF
|
||||
#define KEYSLOT_HWPARTITION_ID 2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMX_TRUSTY_OS
|
||||
#define NON_SECURE_FASTBOOT
|
||||
#define TRUSTY_KEYSLOT_PACKAGE
|
||||
#endif
|
||||
#include "mx_android_common.h"
|
||||
|
||||
|
||||
/* For NAND we don't support lock/unlock */
|
||||
#ifndef CONFIG_NAND_BOOT
|
||||
#define CONFIG_FASTBOOT_LOCK
|
||||
#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
|
||||
#define FSL_FASTBOOT_FB_DEV "mmc"
|
||||
#endif
|
||||
|
||||
#define CONFIG_ANDROID_AB_SUPPORT
|
||||
|
||||
#define CONFIG_FSL_CAAM_KB
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
|
||||
#define CONFIG_SYSTEM_RAMDISK_SUPPORT
|
||||
#define CONFIG_AVB_SUPPORT
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_DEV
|
||||
#undef CONFIG_SYS_MMC_ENV_DEV
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_PART
|
||||
#undef CONFIG_SYS_MMC_ENV_PART
|
||||
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_AVB_SUPPORT
|
||||
#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
|
||||
#ifdef CONFIG_SYS_MALLOC_LEN
|
||||
#undef CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
#endif
|
||||
/* fuse bank size in word */
|
||||
/* infact 7D have no enough bits
|
||||
* set this size to 0 will disable
|
||||
* program/read FUSE */
|
||||
#define CONFIG_AVB_FUSE_BANK_SIZEW 4
|
||||
#define CONFIG_AVB_FUSE_BANK_START 14
|
||||
#define CONFIG_AVB_FUSE_BANK_END 14
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* __PICO_IMX7DANDROIDTHINGS_H */
|
||||
Loading…
Reference in New Issue