MLK-15324-2 video: imxdpuv1: Add DPU driver for i.MX8
Adding new IMXDPUV1 (aka Seeris, Iris-lite) display control driver. Signed-off-by: Oliver Brown <oliver.brown@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 43541cba14f851c6eebaa84becd42967f94a9cfd)
This commit is contained in:
Ye Li
parent
8a2330424c
commit
02b99a8ce3
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@ -513,6 +513,13 @@ config VIDEO_IPUV3
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This enables framebuffer driver for i.MX processors working
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on the IPUv3(Image Processing Unit) internal graphic processor.
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config VIDEO_IMXDPUV1
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bool "i.MX DPU V1 display support"
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default n
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depends on VIDEO && IMX8
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help
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Support for IMXDPU V1 display controller for i.MX8 processors.
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config MXC_EPDC
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bool "i.MX EPDC support"
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depends on LCD && (MX7 || MX6)
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@ -41,6 +41,7 @@ obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
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obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
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obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
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obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
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obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o
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obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
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obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
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obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,116 @@
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/*
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* Copyright (c) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef IMXDPUV1_BE_H
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#define IMXDPUV1_BE_H
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struct fetch_unit {
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uint32_t in_pipeline;
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uint32_t control;
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uint32_t burst_buf;
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uint32_t buf_address;
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uint32_t buf_attributes;
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uint32_t buf_dimension;
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uint32_t color_bits;
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uint32_t color_shift;
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uint32_t layer_offset;
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uint32_t clip_offset;
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uint32_t clip_dimension;
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uint32_t const_color;
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uint32_t layer_property;
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uint32_t frame_dimension;
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uint32_t frame_resample;
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};
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struct store_unit {
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uint32_t in_pipeline;
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uint32_t control;
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uint32_t burst_buf;
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uint32_t buf_address;
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uint32_t buf_attributes;
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uint32_t buf_dimension;
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uint32_t frame_offset;
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uint32_t color_bits;
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uint32_t color_shift;
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};
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struct rop_unit {
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uint32_t in_pipeline;
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uint32_t control;
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};
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struct matrix_unit {
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uint32_t in_pipeline;
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uint32_t control;
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};
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struct hscaler_unit {
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uint32_t in_pipeline;
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uint32_t control;
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uint32_t setup1;
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uint32_t setup2;
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};
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struct vscaler_unit {
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uint32_t in_pipeline;
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uint32_t control;
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uint32_t setup1;
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uint32_t setup2;
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uint32_t setup3;
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uint32_t setup4;
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uint32_t setup5;
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};
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struct blitblend_unit {
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uint32_t in_pipeline;
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uint32_t control;
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uint32_t const_color;
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uint32_t red_func;
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uint32_t green_func;
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uint32_t blue_func;
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uint32_t alpha_func;
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uint32_t blend_mode1;
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uint32_t blend_mode2;
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};
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struct engcfg_unit {
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uint32_t fetchpersp9_dynamic;
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uint32_t fetchdecode9_dynamic;
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uint32_t rop9_dynamic;
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uint32_t matrix9_dynamic;
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uint32_t hscaler9_dynamic;
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uint32_t vscaler9_dynamic;
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uint32_t blitblend9_dynamic;
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uint32_t store9_dynamic;
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};
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struct be_blit_cfg {
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struct fetch_unit fetch_decode;
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struct fetch_unit fetch_persp;
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struct fetch_unit fetch_eco;
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struct store_unit store;
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struct rop_unit rop;
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struct matrix_unit matrix;
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struct hscaler_unit hscaler;
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struct vscaler_unit vscaler;
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struct blitblend_unit blitblend;
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struct engcfg_unit engcfg;
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};
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/* PRIVATE DATA */
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struct imxdpuv1_info {
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/*reg */
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void __iomem *base;
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};
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#define IMXDPUV1_IOC_MAGIC 'i'
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#define IMXDPUV1_IOC_BLIT _IOW(IMXDPUV1_IOC_MAGIC, 1, struct be_blit_cfg)
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#define IMXDPUV1_IOC_WAIT _IO(IMXDPUV1_IOC_MAGIC, 2)
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void imxdpuv1_be_irq_handler(int8_t imxdpuv1_id, int8_t irq);
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int imxdpuv1_be_init(int8_t imxdpuv1_id, void __iomem *imxdpuv1_base);
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int imxdpuv1_be_blit(struct imxdpuv1_info *imxdpu, struct be_blit_cfg *cfg);
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int imxdpuv1_be_wait_shadow_load(struct imxdpuv1_info *imxdpu);
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int imxdpuv1_be_wait_complete(struct imxdpuv1_info *imxdpu);
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int imxdpuv1_be_load(struct imxdpuv1_info *imxdpu, void __user *p);
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int imxdpuv1_be_wait(struct imxdpuv1_info *imxdpu);
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#endif
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@ -0,0 +1,470 @@
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/*
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* Copyright (c) 2005-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Instance: imxdpuv1_private.h */
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#ifndef IMXDPUV1_PRIVATE_H
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#define IMXDPUV1_PRIVATE_H
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#include <asm/io.h>
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#include <asm/string.h>
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#include <linux/types.h>
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#include "imxdpuv1.h"
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typedef enum {
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IMXDPUV1_BURST_UNKNOWN = 0,
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IMXDPUV1_BURST_LEFT_RIGHT_DOWN,
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IMXDPUV1_BURST_HORIZONTAL,
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IMXDPUV1_BURST_VERTICAL,
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IMXDPUV1_BURST_FREE,
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} imxdpuv1_burst_t;
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#define INTSTAT0_BIT(__bit__) (1U<<(__bit__))
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#define INTSTAT1_BIT(__bit__) (1U<<((__bit__)-32))
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#define INTSTAT2_BIT(__bit__) (1U<<((__bit__)-64))
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struct imxdpuv1_irq_node {
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int(*handler) (int, void *);
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const char *name;
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void *data;
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uint32_t flags;
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};
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/* Generic definitions that are common to many registers */
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#define IMXDPUV1_COLOR_BITSALPHA0_MASK 0xFU
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#define IMXDPUV1_COLOR_BITSALPHA0_SHIFT 0U
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#define IMXDPUV1_COLOR_BITSBLUE0_MASK 0xF00U
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#define IMXDPUV1_COLOR_BITSBLUE0_SHIFT 8U
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#define IMXDPUV1_COLOR_BITSGREEN0_MASK 0xF0000U
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#define IMXDPUV1_COLOR_BITSGREEN0_SHIFT 16U
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#define IMXDPUV1_COLOR_BITSRED0_MASK 0xF000000U
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#define IMXDPUV1_COLOR_BITSRED0_SHIFT 24U
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#define IMXDPUV1_COLOR_SHIFTALPHA0_MASK 0x1FU
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#define IMXDPUV1_COLOR_SHIFTALPHA0_SHIFT 0U
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#define IMXDPUV1_COLOR_SHIFTBLUE0_MASK 0x1F00U
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#define IMXDPUV1_COLOR_SHIFTBLUE0_SHIFT 8U
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#define IMXDPUV1_COLOR_SHIFTGREEN0_MASK 0x1F0000U
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#define IMXDPUV1_COLOR_SHIFTGREEN0_SHIFT 16U
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#define IMXDPUV1_COLOR_SHIFTRED0_MASK 0x1F000000U
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#define IMXDPUV1_COLOR_SHIFTRED0_SHIFT 24U
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#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU
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#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U
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#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U
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#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U
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#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U
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#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U
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#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U
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#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U
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/* these are common for fetch but not store */
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#define IMXDPUV1_BUFF_ATTR_STRIDE_MASK 0xFFFFU
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#define IMXDPUV1_BUFF_ATTR_STRIDE_SHIFT 0U
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#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_MASK 0x3F0000U
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#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_SHIFT 16U
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#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_SHIFT 16U
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#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_MASK 0x3FFFU
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#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_SHIFT 0U
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#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_MASK 0x3FFF0000U
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#define IMXDPUV1_LAYER_XOFFSET_MASK 0x7FFFU
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#define IMXDPUV1_LAYER_XOFFSET_SHIFT 0U
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#define IMXDPUV1_LAYER_XSBIT_MASK 0x4000U
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#define IMXDPUV1_LAYER_XSBIT_SHIFT 0U
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#define IMXDPUV1_LAYER_YOFFSET_MASK 0x7FFF0000U
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#define IMXDPUV1_LAYER_YOFFSET_SHIFT 16U
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#define IMXDPUV1_LAYER_YSBIT_MASK 0x4000U
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#define IMXDPUV1_LAYER_YSBIT_SHIFT 16U
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#define IMXDPUV1_CLIP_XOFFSET_MASK 0x7FFFU
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#define IMXDPUV1_CLIP_XOFFSET_SHIFT 0U
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#define IMXDPUV1_CLIP_YOFFSET_MASK 0x7FFF0000U
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#define IMXDPUV1_CLIP_YOFFSET_SHIFT 16U
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#define IMXDPUV1_CLIP_WIDTH_MASK 0x3FFFU
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#define IMXDPUV1_CLIP_WIDTH_SHIFT 0U
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#define IMXDPUV1_CLIP_HEIGHT_MASK 0x3FFF0000U
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#define IMXDPUV1_CLIP_HEIGHT_SHIFT 16U
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#define IMXDPUV1_FRAMEWIDTH_MASK 0x3FFFU
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#define IMXDPUV1_FRAMEWIDTH_SHIFT 0U
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#define IMXDPUV1_FRAMEHEIGHT_MASK 0x3FFF0000U
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#define IMXDPUV1_FRAMEHEIGHT_SHIFT 16U
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#define IMXDPUV1_EMPTYFRAME_MASK 0x80000000U
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#define IMXDPUV1_EMPTYFRAME_SHIFT 31U
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#define IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE 0U
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#define IMXDPUV1_PIXENGCFG_SRC_SEL_MASK 0x3FU
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#define IMXDPUV1_PIXENGCFG_SRC_SEL_SHIFT 0U
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_MASK 0x3FU
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_SHIFT 0U
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE 0U
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_MASK 0x3F00U
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_SHIFT 8U
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#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE 0U
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#define IMXDPUV1_PIXENGCFG_CLKEN_MASK 0x3000000U
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#define IMXDPUV1_PIXENGCFG_CLKEN_SHIFT 24U
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/* Field Value: _CLKEN__DISABLE, Clock for block is disabled */
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#define IMXDPUV1_PIXENGCFG_CLKEN__DISABLE 0U
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/* Field Value: _CLKEN__AUTOMATIC, Clock is enabled if unit is used,
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* frequency is defined by the register setting for this pipeline (see
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* [endpoint_name]_Static register) */
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#define IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC 0x1U
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/* Field Value: _CLKEN__FULL, Clock for block is without gating */
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#define IMXDPUV1_PIXENGCFG_CLKEN__FULL 0x3U
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/* Register: IMXDPUV1_LayerProperty0 Common Bits */
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#define IMXDPUV1_LAYERPROPERTY_OFFSET ((uint32_t)(0x40))
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#define IMXDPUV1_LAYERPROPERTY_RESET_VALUE 0x80000100U
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#define IMXDPUV1_LAYERPROPERTY_RESET_MASK 0xFFFFFFFFU
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#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U
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#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_SHIFT 0U
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE_MASK 0x30U
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE_SHIFT 4U
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/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_ZERO 0U
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/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
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* value */
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_CONSTANT 0x1U
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/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
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* Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
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* is 0. */
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD 0x2U
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/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
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* but zero for alpha component. Must not be used for DECODE or YUV422
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* operations or when SourceBufferEnable is 0. */
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#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD_ZERO 0x3U
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#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_MASK 0x100U
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#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_SHIFT 8U
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#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_MASK 0x200U
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#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_SHIFT 9U
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#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_MASK 0x400U
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#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_SHIFT 10U
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#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_MASK 0x800U
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#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_SHIFT 11U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_MASK 0x1000U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_SHIFT 12U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_MASK 0x2000U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_SHIFT 13U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_MASK 0x4000U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_SHIFT 14U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_MASK 0x8000U
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#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_SHIFT 15U
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#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_MASK 0x10000U
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#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_SHIFT 16U
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_MASK 0x60000U
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_SHIFT 17U
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/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF 0U
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/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
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* RGB according to ITU recommendation BT.601-6 (standard definition TV).
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* Input range is 16..235 for Y and 16..240 for U/V. */
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601 0x1U
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/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
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* to RGB according to ITU recommendation BT.601-6, but assuming full range
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* YUV inputs (0..255). Most typically used for computer graphics (e.g.
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* for JPEG encoding). */
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601_FR 0x2U
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/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
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* RGB according to ITU recommendation BT.709-5 part 2 (high definition
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* TV). Input range is 16..235 for Y and 16..240 for U/V. */
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#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU709 0x3U
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#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_MASK 0x100000U
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#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_SHIFT 20U
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#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U
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#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_SHIFT 30U
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#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U
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#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_SHIFT 31U
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typedef struct {
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/* Source buffer base address of layer 0. */
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uint32_t baseaddress0;
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/* Source buffer attributes for layer 0. */
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uint32_t sourcebufferattributes0;
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/* Source buffer dimension of layer 0. */
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uint32_t sourcebufferdimension0;
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/* Size of color components for RGB, YUV and index formats (layer 0). */
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uint32_t colorcomponentbits0;
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/* Bit position of color components for RGB, YUV and index
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formats (layer 0). */
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uint32_t colorcomponentshift0;
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/* Position of layer 0 within the destination frame. */
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uint32_t layeroffset0;
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/* Clip window position for layer 0. */
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uint32_t clipwindowoffset0;
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/* Clip window size for layer 0. */
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uint32_t clipwindowdimensions0;
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/* Constant color for layer 0. */
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uint32_t constantcolor0;
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/* Common properties of layer 0. */
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uint32_t layerproperty0;
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} fetch_layer_setup_t;
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typedef struct {
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/* Destination buffer base address of layer 0. */
|
||||
uint32_t baseaddress0;
|
||||
/* Destination buffer attributes for layer 0. */
|
||||
uint32_t destbufferattributes0;
|
||||
/* Source buffer dimension of layer 0. */
|
||||
uint32_t destbufferdimension0;
|
||||
/* Frame offset of layer 0. */
|
||||
uint32_t frameoffset0;
|
||||
/* Size of color components for RGB, YUV and index formats (layer 0). */
|
||||
uint32_t colorcomponentbits0;
|
||||
/* Bit position of color components for RGB, YUV and index
|
||||
formats (layer 0). */
|
||||
uint32_t colorcomponentshift0;
|
||||
} store_layer_setup_t;
|
||||
|
||||
typedef enum {
|
||||
IMXDPUV1_SHDLD_IDX_DISP0 = (0),
|
||||
IMXDPUV1_SHDLD_IDX_DISP1 = (1),
|
||||
IMXDPUV1_SHDLD_IDX_CONST0 = (2), /* IMXDPUV1_ID_CONSTFRAME0 */
|
||||
IMXDPUV1_SHDLD_IDX_CONST1 = (3), /* IMXDPUV1_ID_CONSTFRAME1 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_00 = (4), /* IMXDPUV1_ID_FETCHDECODE2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_01 = (5), /* IMXDPUV1_ID_FETCHDECODE0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_02 = (6), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_03 = (7), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_04 = (8), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_05 = (9), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_06 = (10), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_07 = (11), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_08 = (12), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_09 = (13), /* IMXDPUV1_ID_FETCHLAYER0 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_10 = (14), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_11 = (15), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_12 = (16), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_13 = (17), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_14 = (18), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_15 = (19), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_16 = (20), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_17 = (21), /* IMXDPUV1_ID_FETCHWARP2 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_18 = (22), /* IMXDPUV1_ID_FETCHDECODE3 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_19 = (23), /* IMXDPUV1_ID_FETCHDECODE1 */
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_20 = (24), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_21 = (25), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_22 = (26), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_23 = (27), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_24 = (28), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_25 = (29), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_26 = (30), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_27 = (31), /* IMXDPUV1_ID_FETCHLAYER1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_28 = (32), /* IMXDPUV1_ID_FETCHECO0*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_29 = (33), /* IMXDPUV1_ID_FETCHECO1*/
|
||||
IMXDPUV1_SHDLD_IDX_CHAN_30 = (34), /* IMXDPUV1_ID_FETCHECO2*/
|
||||
IMXDPUV1_SHDLD_IDX_MAX = (35),
|
||||
} imxdpuv1_shadow_load_index_t;
|
||||
|
||||
typedef struct {
|
||||
bool prim_sync_state;
|
||||
bool sec_sync_state;
|
||||
uint32_t prim_sync_count;
|
||||
uint32_t sec_sync_count;
|
||||
uint32_t skew_error_count;
|
||||
uint32_t prim_fifo_empty_count;
|
||||
uint32_t sec_fifo_empty_count;
|
||||
uint32_t frame_count;
|
||||
} frame_gen_stats_t;
|
||||
|
||||
/*!
|
||||
* Definition of IMXDPU channel structure
|
||||
*/
|
||||
typedef struct {
|
||||
int8_t disp_id; /* Iris instance id of "owner" */
|
||||
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
int16_t src_top;
|
||||
int16_t src_left;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint16_t const_color;
|
||||
|
||||
uint32_t h_scale_factor; /* downscaling out/in */
|
||||
uint32_t h_phase;
|
||||
uint32_t v_scale_factor; /* downscaling out/in */
|
||||
uint32_t v_phase[2][2];
|
||||
|
||||
bool use_video_proc;
|
||||
bool interlaced;
|
||||
bool use_eco_fetch;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
|
||||
/* note: dma_addr_t changes for 64-bit arch */
|
||||
dma_addr_t phyaddr_0;
|
||||
|
||||
uint32_t u_offset;
|
||||
uint32_t v_offset;
|
||||
|
||||
uint8_t blend_layer;
|
||||
uint8_t destination_stream;
|
||||
uint8_t source_id;
|
||||
|
||||
imxdpuv1_rotate_mode_t rot_mode;
|
||||
|
||||
/* todo add features sub-windows, upscaling, warping */
|
||||
fetch_layer_setup_t fetch_layer_prop;
|
||||
store_layer_setup_t store_layer_prop;
|
||||
|
||||
bool in_use;
|
||||
|
||||
/* todo: add channel features */
|
||||
} chan_private_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t request;
|
||||
uint8_t processing;
|
||||
uint8_t complete;
|
||||
uint8_t trys;
|
||||
} state;
|
||||
uint32_t word;
|
||||
} imxdpuv1_shadow_state_t;
|
||||
|
||||
/* PRIVATE DATA */
|
||||
struct imxdpuv1_soc {
|
||||
int8_t devtype;
|
||||
int8_t online;
|
||||
uint32_t enabled_int[3];
|
||||
struct imxdpuv1_irq_node irq_list[IMXDPUV1_INTERRUPT_MAX];
|
||||
|
||||
struct device *dev;
|
||||
struct imxdpuv1_videomode video_mode[IMXDPUV1_NUM_DI];
|
||||
struct imxdpuv1_videomode capture_mode[IMXDPUV1_NUM_CI];
|
||||
frame_gen_stats_t fgen_stats[IMXDPUV1_NUM_DI];
|
||||
uint32_t irq_count;
|
||||
|
||||
|
||||
/*
|
||||
* Bypass reset to avoid display channel being
|
||||
* stopped by probe since it may starts to work
|
||||
* in bootloader.
|
||||
*/
|
||||
int8_t bypass_reset;
|
||||
|
||||
/* todo: need to decide where the locking is implemented */
|
||||
|
||||
/*clk*/
|
||||
|
||||
/*irq*/
|
||||
|
||||
/*reg*/
|
||||
void __iomem *base;
|
||||
|
||||
/*use count*/
|
||||
imxdpuv1_layer_t blend_layer[IMXDPUV1_LAYER_MAX];
|
||||
chan_private_t chan_data[IMXDPUV1_CHAN_IDX_MAX];
|
||||
|
||||
uint8_t shadow_load_pending[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX];
|
||||
imxdpuv1_shadow_state_t shadow_load_state[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX];
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* PRIVATE FUNCTIONS */
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_REG
|
||||
uint32_t _imxdpuv1_read(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line);
|
||||
#define imxdpuv1_read(_inst_, _offset_) _imxdpuv1_read(_inst_, _offset_, __FILE__, __LINE__)
|
||||
#else
|
||||
static inline uint32_t imxdpuv1_read(struct imxdpuv1_soc *dpu, uint32_t offset)
|
||||
{
|
||||
return __raw_readl(dpu->base + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ
|
||||
uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line);
|
||||
#define imxdpuv1_read_irq(_inst_, _offset_) _imxdpuv1_read_irq(_inst_, _offset_, __FILE__, __LINE__)
|
||||
#else
|
||||
static inline uint32_t imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, uint32_t offset)
|
||||
{
|
||||
return __raw_readl(dpu->base + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_REG
|
||||
void _imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line);
|
||||
#define imxdpuv1_write(_inst_, _value_, _offset_) _imxdpuv1_write(_inst_, _value_, _offset_, __FILE__, __LINE__)
|
||||
#else
|
||||
static inline void imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value)
|
||||
{
|
||||
__raw_writel(value, dpu->base + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE
|
||||
void _imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line);
|
||||
#define imxdpuv1_write_irq(_inst_, _value_, _offset_) _imxdpuv1_write_irq(_inst_, _value_, _offset_, __FILE__, __LINE__)
|
||||
#else
|
||||
static inline void imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value)
|
||||
{
|
||||
__raw_writel(value, dpu->base + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, void *values, uint32_t cnt, char *file, int line);
|
||||
#define imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_) _imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_, __FILE__, __LINE__)
|
||||
|
||||
/* mapping of RGB, Tcon, or static values to output */
|
||||
#define IMXDPUV1_TCON_MAPBIT__RGB(_x_) ((_x_))
|
||||
#define IMXDPUV1_TCON_MAPBIT__Tsig(_x_) ((_x_) + 30)
|
||||
#define IMXDPUV1_TCON_MAPBIT__HIGH 42U
|
||||
#define IMXDPUV1_TCON_MAPBIT__LOW 43U
|
||||
|
||||
/* these match the bit definitions for the shadlow load
|
||||
request registers
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_SHLDREQID_FETCHDECODE9 = 0,
|
||||
IMXDPUV1_SHLDREQID_FETCHPERSP9,
|
||||
IMXDPUV1_SHLDREQID_FETCHECO9,
|
||||
IMXDPUV1_SHLDREQID_CONSTFRAME0,
|
||||
IMXDPUV1_SHLDREQID_CONSTFRAME4,
|
||||
IMXDPUV1_SHLDREQID_CONSTFRAME1,
|
||||
IMXDPUV1_SHLDREQID_CONSTFRAME5,
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
IMXDPUV1_SHLDREQID_EXTSRC4,
|
||||
IMXDPUV1_SHLDREQID_EXTSRC5,
|
||||
IMXDPUV1_SHLDREQID_FETCHDECODE2,
|
||||
IMXDPUV1_SHLDREQID_FETCHDECODE3,
|
||||
#endif
|
||||
IMXDPUV1_SHLDREQID_FETCHWARP2,
|
||||
IMXDPUV1_SHLDREQID_FETCHECO2,
|
||||
IMXDPUV1_SHLDREQID_FETCHDECODE0,
|
||||
IMXDPUV1_SHLDREQID_FETCHECO0,
|
||||
IMXDPUV1_SHLDREQID_FETCHDECODE1,
|
||||
IMXDPUV1_SHLDREQID_FETCHECO1,
|
||||
IMXDPUV1_SHLDREQID_FETCHLAYER0,
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
IMXDPUV1_SHLDREQID_FETCHLAYER1,
|
||||
IMXDPUV1_SHLDREQID_EXTSRC0,
|
||||
IMXDPUV1_SHLDREQID_EXTSRC1
|
||||
#endif
|
||||
} imxdpuv1_shadow_load_req_t;
|
||||
|
||||
#define IMXDPUV1_PIXENGCFG_DIVIDER_RESET 0x80
|
||||
|
||||
#endif /* IMXDPUV1_PRIVATE_H */
|
||||
|
||||
|
|
@ -0,0 +1,998 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef IMXDPUV1_H
|
||||
#define IMXDPUV1_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <errno.h>
|
||||
|
||||
/* these will be removed */
|
||||
#undef IMXDPUV1_VERSION_0
|
||||
#define IMXDPUV1_VERSION_1
|
||||
|
||||
/* #define DEBUG */
|
||||
/* #define ENABLE_IMXDPUV1_TRACE */
|
||||
/* #define ENABLE_IMXDPUV1_TRACE_REG */
|
||||
/* #define ENABLE_IMXDPUV1_TRACE_IRQ */
|
||||
/* #define ENABLE_IMXDPUV1_TRACE_IRQ_READ */
|
||||
/* #define ENABLE_IMXDPUV1_TRACE_IRQ_WRITE */
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE
|
||||
#define IMXDPUV1_TRACE(fmt, ...) \
|
||||
printf((fmt), ##__VA_ARGS__)
|
||||
#else
|
||||
#define IMXDPUV1_TRACE(fmt, ...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_IRQ
|
||||
#define IMXDPUV1_TRACE_IRQ(fmt, ...) \
|
||||
printf((fmt), ##__VA_ARGS__)
|
||||
#else
|
||||
#define IMXDPUV1_TRACE_IRQ(fmt, ...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_IMXDPUV1_TRACE_REG
|
||||
#define IMXDPUV1_TRACE_REG(fmt, ...) \
|
||||
printf((fmt), ##__VA_ARGS__)
|
||||
#else
|
||||
#define IMXDPUV1_TRACE_REG(fmt, ...) do {} while (0)
|
||||
#endif
|
||||
|
||||
#define IMXDPUV1_PRINT(fmt, ...) \
|
||||
printf((fmt), ##__VA_ARGS__)
|
||||
|
||||
/* #define IMXDPUV1_TCON0_MAP_24BIT_0_23 */
|
||||
/* #define IMXDPUV1_TCON1_MAP_24BIT_0_23 */
|
||||
|
||||
/* todo: this need to come from device tree */
|
||||
#define IMXDPUV1_NUM_DI_MAX 2
|
||||
#define IMXDPUV1_MAX_NUM 2
|
||||
#define IMXDPUV1_NUM_DI 2
|
||||
#define IMXDPUV1_NUM_CI 2
|
||||
#define IMXDPUV1_REGS_BASE_PHY0 0x56180000
|
||||
#define IMXDPUV1_REGS_BASE_PHY1 0x57180000
|
||||
#define IMXDPUV1_REGS_BASE_SIZE 0x14000
|
||||
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
#define IMXDPUV1_ENABLE_INTSTAT2
|
||||
#endif
|
||||
#define IMXDPUV1_SET_FIELD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
|
||||
#define IMXDPUV1_GET_FIELD(field, reg) (((reg)&(field ## _MASK)) >> (field ## _SHIFT))
|
||||
|
||||
/*
|
||||
IMXDPU windows, planes, layers, streams
|
||||
|
||||
IMXDPU hardware documentation confuses the meaning of layers and
|
||||
planes. These are software usages of these terms.
|
||||
|
||||
window - a logical buffer of pixels in a rectangular arrangment.
|
||||
Image, Integral and video planes suport one window.
|
||||
Fractional and warp plane support 8 windows. Blending is not
|
||||
supported between the sub-windows of a fractional or warp plane.
|
||||
|
||||
sub-window - one of the eight logical windows of a fractional or warp
|
||||
plane.
|
||||
|
||||
channel - the logical DMA configuration for etiher a fetch or store unit
|
||||
|
||||
plane - a plane is a hardware supported feature. There are four types
|
||||
of display planes:
|
||||
|
||||
video x2
|
||||
fractional x2
|
||||
intergral x2
|
||||
warp
|
||||
|
||||
layer - each of the 7 planes is fed to a layer blender. Full Alpha
|
||||
blending is supported for all of the planes fed to the layer
|
||||
blender.
|
||||
|
||||
streams - the layer bleder produces four streams: two normal streams
|
||||
(0 and 1) and two panic streams (4 and 5).
|
||||
|
||||
In normal mode, streams 0 and 1 are fed to the displays.
|
||||
In panic mode, streams 4 and 5 are fed to the displays.
|
||||
*/
|
||||
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU blend mode flags
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_PLANE_CLUT = 1 << 0, /* Color lookup */
|
||||
IMXDPUV1_PLANE_DECODE = 1 << 1, /* Decode compressed bufers */
|
||||
IMXDPUV1_PLANE_ETERNAL_ALPHA = 1 << 2, /* supports external alpha buffer */
|
||||
IMXDPUV1_PLANE_VIDEO_PROC = 1 << 2, /* Gamma, Matrix, Scaler, histogram */
|
||||
IMXDPUV1_PLANE_PLANAR = 1 << 3, /* Support Planar pixel buffers*/
|
||||
IMXDPUV1_PLANE_WARP = 1 << 4, /* Warping */
|
||||
IMXDPUV1_PLANE_MULTIWINDOW = 1 << 5, /* Support multiple buffers per plane */
|
||||
IMXDPUV1_PLANE_CAPTURE = 1 << 6, /* Video capture */
|
||||
} imxdpuv1_plane_features_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU layer blend mode flags
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_LAYER_NONE = 1 << 0, /* Disable blending */
|
||||
IMXDPUV1_LAYER_TRANSPARENCY = 1 << 1, /* Transparency */
|
||||
IMXDPUV1_LAYER_GLOBAL_ALPHA = 1 << 2, /* Global alpha mode */
|
||||
IMXDPUV1_LAYER_LOCAL_ALPHA = 1 << 3, /* Alpha contained in source buffer */
|
||||
IMXDPUV1_LAYER_EXTERN_ALPHA = 1 << 4, /* Alpha is contained in a separate plane */
|
||||
IMXDPUV1_LAYER_PRE_MULITPLY = 1 << 5, /* Pre-multiply alpha mode */
|
||||
} imxdpuv1_layer_blend_modes_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU layers
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_LAYER_0 = 0,
|
||||
IMXDPUV1_LAYER_1,
|
||||
IMXDPUV1_LAYER_2,
|
||||
IMXDPUV1_LAYER_3,
|
||||
IMXDPUV1_LAYER_4,
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
IMXDPUV1_LAYER_5,
|
||||
IMXDPUV1_LAYER_6,
|
||||
#endif
|
||||
IMXDPUV1_LAYER_MAX,
|
||||
} imxdpuv1_layer_idx_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU sub-windows
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_SUBWINDOW_NONE = 0,
|
||||
IMXDPUV1_SUBWINDOW_1,
|
||||
IMXDPUV1_SUBWINDOW_2,
|
||||
IMXDPUV1_SUBWINDOW_3,
|
||||
IMXDPUV1_SUBWINDOW_4,
|
||||
IMXDPUV1_SUBWINDOW_5,
|
||||
IMXDPUV1_SUBWINDOW_6,
|
||||
IMXDPUV1_SUBWINDOW_7,
|
||||
IMXDPUV1_SUBWINDOW_8,
|
||||
} imxdpuv1_subwindow_id_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU display streams
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_DISPLAY_STREAM_NONE = (0),
|
||||
IMXDPUV1_DISPLAY_STREAM_0 = (1U<<0),
|
||||
IMXDPUV1_DISPLAY_STREAM_1 = (1U<<1),
|
||||
IMXDPUV1_DISPLAY_STREAM_4 = (1U<<4),
|
||||
IMXDPUV1_DISPLAY_STREAM_5 = (1U<<5),
|
||||
} imxdpuv1_display_stream_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU rotation modes
|
||||
*/
|
||||
typedef enum {
|
||||
/* todo: these need to aligh to imxdpu scan direction */
|
||||
IMXDPUV1_ROTATE_NONE = 0,
|
||||
IMXDPUV1_ROTATE_VERT_FLIP = 1,
|
||||
IMXDPUV1_ROTATE_HORIZ_FLIP = 2,
|
||||
IMXDPUV1_ROTATE_180 = 3,
|
||||
IMXDPUV1_ROTATE_90_RIGHT = 4,
|
||||
IMXDPUV1_ROTATE_90_RIGHT_VFLIP = 5,
|
||||
IMXDPUV1_ROTATE_90_RIGHT_HFLIP = 6,
|
||||
IMXDPUV1_ROTATE_90_LEFT = 7,
|
||||
} imxdpuv1_rotate_mode_t;
|
||||
|
||||
|
||||
/*!
|
||||
* Enumeration of types of buffers for a logical channel.
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_OUTPUT_BUFFER = 0, /*!< Buffer for output from IMXDPU BLIT or capture */
|
||||
IMXDPUV1_ALPHA_IN_BUFFER = 1, /*!< Buffer for alpha input to IMXDPU */
|
||||
IMXDPUV1_GRAPH_IN_BUFFER = 2, /*!< Buffer for graphics input to IMXDPU */
|
||||
IMXDPUV1_VIDEO_IN_BUFFER = 3, /*!< Buffer for video input to IMXDPU */
|
||||
} imxdpuv1_buffer_t;
|
||||
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
/*!
|
||||
* Enumeration of IMXDPU logical block ids
|
||||
* NOTE: these match the hardware layout and are not arbitrary
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_ID_NONE = 0,
|
||||
IMXDPUV1_ID_FETCHDECODE9,
|
||||
IMXDPUV1_ID_FETCHPERSP9,
|
||||
IMXDPUV1_ID_FETCHECO9,
|
||||
IMXDPUV1_ID_ROP9,
|
||||
IMXDPUV1_ID_CLUT9,
|
||||
IMXDPUV1_ID_MATRIX9,
|
||||
IMXDPUV1_ID_HSCALER9,
|
||||
IMXDPUV1_ID_VSCALER9,
|
||||
IMXDPUV1_ID_FILTER9,
|
||||
IMXDPUV1_ID_BLITBLEND9,
|
||||
IMXDPUV1_ID_STORE9,
|
||||
IMXDPUV1_ID_CONSTFRAME0,
|
||||
IMXDPUV1_ID_EXTDST0,
|
||||
IMXDPUV1_ID_CONSTFRAME4,
|
||||
IMXDPUV1_ID_EXTDST4,
|
||||
IMXDPUV1_ID_CONSTFRAME1,
|
||||
IMXDPUV1_ID_EXTDST1,
|
||||
IMXDPUV1_ID_CONSTFRAME5,
|
||||
IMXDPUV1_ID_EXTDST5,
|
||||
IMXDPUV1_ID_EXTSRC4,
|
||||
IMXDPUV1_ID_STORE4,
|
||||
IMXDPUV1_ID_EXTSRC5,
|
||||
IMXDPUV1_ID_STORE5,
|
||||
IMXDPUV1_ID_FETCHDECODE2,
|
||||
IMXDPUV1_ID_FETCHDECODE3,
|
||||
IMXDPUV1_ID_FETCHWARP2,
|
||||
IMXDPUV1_ID_FETCHECO2,
|
||||
IMXDPUV1_ID_FETCHDECODE0,
|
||||
IMXDPUV1_ID_FETCHECO0,
|
||||
IMXDPUV1_ID_FETCHDECODE1,
|
||||
IMXDPUV1_ID_FETCHECO1,
|
||||
IMXDPUV1_ID_FETCHLAYER0,
|
||||
IMXDPUV1_ID_FETCHLAYER1,
|
||||
IMXDPUV1_ID_GAMMACOR4,
|
||||
IMXDPUV1_ID_MATRIX4,
|
||||
IMXDPUV1_ID_HSCALER4,
|
||||
IMXDPUV1_ID_VSCALER4,
|
||||
IMXDPUV1_ID_HISTOGRAM4,
|
||||
IMXDPUV1_ID_GAMMACOR5,
|
||||
IMXDPUV1_ID_MATRIX5,
|
||||
IMXDPUV1_ID_HSCALER5,
|
||||
IMXDPUV1_ID_VSCALER5,
|
||||
IMXDPUV1_ID_HISTOGRAM5,
|
||||
IMXDPUV1_ID_LAYERBLEND0,
|
||||
IMXDPUV1_ID_LAYERBLEND1,
|
||||
IMXDPUV1_ID_LAYERBLEND2,
|
||||
IMXDPUV1_ID_LAYERBLEND3,
|
||||
IMXDPUV1_ID_LAYERBLEND4,
|
||||
IMXDPUV1_ID_LAYERBLEND5,
|
||||
IMXDPUV1_ID_LAYERBLEND6,
|
||||
IMXDPUV1_ID_EXTSRC0,
|
||||
IMXDPUV1_ID_EXTSRC1,
|
||||
IMXDPUV1_ID_DISENGCFG,
|
||||
IMXDPUV1_ID_FRAMEDUMP0,
|
||||
IMXDPUV1_ID_FRAMEDUMP1,
|
||||
IMXDPUV1_ID_FRAMEGEN0,
|
||||
IMXDPUV1_ID_MATRIX0,
|
||||
IMXDPUV1_ID_GAMMACOR0,
|
||||
IMXDPUV1_ID_DITHER0,
|
||||
IMXDPUV1_ID_TCON0,
|
||||
IMXDPUV1_ID_SIG0,
|
||||
IMXDPUV1_ID_FRAMEGEN1,
|
||||
IMXDPUV1_ID_MATRIX1,
|
||||
IMXDPUV1_ID_GAMMACOR1,
|
||||
IMXDPUV1_ID_DITHER1,
|
||||
IMXDPUV1_ID_TCON1,
|
||||
IMXDPUV1_ID_SIG1,
|
||||
IMXDPUV1_ID_CAPENGCFG,
|
||||
IMXDPUV1_ID_FRAMECAP4,
|
||||
IMXDPUV1_ID_FRAMECAP5,
|
||||
IMXDPUV1_ID_ANALYSER4,
|
||||
IMXDPUV1_ID_ANALYSER5,
|
||||
/* the following are added arbitrarily */
|
||||
IMXDPUV1_ID_DPUXPC,
|
||||
|
||||
} imxdpuv1_id_t;
|
||||
#else
|
||||
/*!
|
||||
* Enumeration of IMXDPU logical block ids
|
||||
* NOTE: these match the hardware layout and are not arbitrary
|
||||
*/
|
||||
typedef enum {
|
||||
IMXDPUV1_ID_NONE = 0,
|
||||
IMXDPUV1_ID_FETCHDECODE9,
|
||||
IMXDPUV1_ID_FETCHWARP9,
|
||||
IMXDPUV1_ID_FETCHECO9,
|
||||
IMXDPUV1_ID_ROP9,
|
||||
IMXDPUV1_ID_CLUT9,
|
||||
IMXDPUV1_ID_MATRIX9,
|
||||
IMXDPUV1_ID_HSCALER9,
|
||||
IMXDPUV1_ID_VSCALER9,
|
||||
IMXDPUV1_ID_FILTER9,
|
||||
IMXDPUV1_ID_BLITBLEND9,
|
||||
IMXDPUV1_ID_STORE9,
|
||||
IMXDPUV1_ID_CONSTFRAME0,
|
||||
IMXDPUV1_ID_EXTDST0,
|
||||
IMXDPUV1_ID_CONSTFRAME4,
|
||||
IMXDPUV1_ID_EXTDST4,
|
||||
IMXDPUV1_ID_CONSTFRAME1,
|
||||
IMXDPUV1_ID_EXTDST1,
|
||||
IMXDPUV1_ID_CONSTFRAME5,
|
||||
IMXDPUV1_ID_EXTDST5,
|
||||
IMXDPUV1_ID_FETCHWARP2,
|
||||
IMXDPUV1_ID_FETCHECO2,
|
||||
IMXDPUV1_ID_FETCHDECODE0,
|
||||
IMXDPUV1_ID_FETCHECO0,
|
||||
IMXDPUV1_ID_FETCHDECODE1,
|
||||
IMXDPUV1_ID_FETCHECO1,
|
||||
IMXDPUV1_ID_FETCHLAYER0,
|
||||
IMXDPUV1_ID_MATRIX4,
|
||||
IMXDPUV1_ID_HSCALER4,
|
||||
IMXDPUV1_ID_VSCALER4,
|
||||
IMXDPUV1_ID_MATRIX5,
|
||||
IMXDPUV1_ID_HSCALER5,
|
||||
IMXDPUV1_ID_VSCALER5,
|
||||
IMXDPUV1_ID_LAYERBLEND0,
|
||||
IMXDPUV1_ID_LAYERBLEND1,
|
||||
IMXDPUV1_ID_LAYERBLEND2,
|
||||
IMXDPUV1_ID_LAYERBLEND3,
|
||||
IMXDPUV1_ID_DISENGCFG,
|
||||
IMXDPUV1_ID_FRAMEGEN0,
|
||||
IMXDPUV1_ID_MATRIX0,
|
||||
IMXDPUV1_ID_GAMMACOR0,
|
||||
IMXDPUV1_ID_DITHER0,
|
||||
IMXDPUV1_ID_TCON0,
|
||||
IMXDPUV1_ID_SIG0,
|
||||
IMXDPUV1_ID_FRAMEGEN1,
|
||||
IMXDPUV1_ID_MATRIX1,
|
||||
IMXDPUV1_ID_GAMMACOR1,
|
||||
IMXDPUV1_ID_DITHER1,
|
||||
IMXDPUV1_ID_TCON1,
|
||||
IMXDPUV1_ID_SIG1,
|
||||
IMXDPUV1_ID_DPUXPC,
|
||||
} imxdpuv1_id_t;
|
||||
#endif
|
||||
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
typedef enum {
|
||||
IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7,
|
||||
IMXDPUV1_SHDLD_EXTSRC4 = 1U << 8,
|
||||
IMXDPUV1_SHDLD_EXTSRC5 = 1U << 9,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE2 = 1U << 10,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE3 = 1U << 11,
|
||||
IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 12,
|
||||
IMXDPUV1_SHDLD_FETCHECO2 = 1U << 13,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 14,
|
||||
IMXDPUV1_SHDLD_FETCHECO0 = 1U << 15,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 16,
|
||||
IMXDPUV1_SHDLD_FETCHECO1 = 1U << 17,
|
||||
IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 18,
|
||||
IMXDPUV1_SHDLD_FETCHLAYER1 = 1U << 19,
|
||||
IMXDPUV1_SHDLD_EXTSRC0 = 1U << 20,
|
||||
IMXDPUV1_SHDLD_EXTSRC1 = 1U << 21,
|
||||
} imxdpuv1_shadow_load_req_id_t;
|
||||
#else
|
||||
typedef enum {
|
||||
IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6,
|
||||
IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7,
|
||||
IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 8,
|
||||
IMXDPUV1_SHDLD_FETCHECO2 = 1U << 9,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 10,
|
||||
IMXDPUV1_SHDLD_FETCHECO0 = 1U << 11,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 12,
|
||||
IMXDPUV1_SHDLD_FETCHECO1 = 1U << 13,
|
||||
IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 14,
|
||||
|
||||
IMXDPUV1_SHDLD_EXTSRC4 = 0,
|
||||
IMXDPUV1_SHDLD_EXTSRC5 = 0,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE2 = 0,
|
||||
IMXDPUV1_SHDLD_FETCHDECODE3 = 0,
|
||||
IMXDPUV1_SHDLD_FETCHLAYER1 = 0,
|
||||
IMXDPUV1_SHDLD_EXTSRC0 = 0,
|
||||
IMXDPUV1_SHDLD_EXTSRC1 = 0,
|
||||
|
||||
} imxdpuv1_shadow_load_req_id_t;
|
||||
|
||||
|
||||
#endif
|
||||
typedef struct {
|
||||
imxdpuv1_id_t primary;
|
||||
imxdpuv1_id_t secondary;
|
||||
imxdpuv1_display_stream_t stream;
|
||||
bool enable;
|
||||
} imxdpuv1_layer_t;
|
||||
|
||||
typedef enum {
|
||||
/* Fetch Channels */
|
||||
IMXDPUV1_CHAN_IDX_IN_FIRST = 0,
|
||||
IMXDPUV1_CHAN_IDX_00 = 0, /* IMXDPUV1_ID_SRC_FETCHDECODE2 */
|
||||
IMXDPUV1_CHAN_IDX_01, /* IMXDPUV1_ID_SRC_FETCHDECODE0 */
|
||||
IMXDPUV1_CHAN_IDX_02, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_03, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_04, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_05, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_06, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_07, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_08, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_09, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */
|
||||
IMXDPUV1_CHAN_IDX_10, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_11, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_12, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_13, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_14, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_15, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_16, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_17, /* IMXDPUV1_ID_SRC_FETCHWARP2 */
|
||||
IMXDPUV1_CHAN_IDX_18, /* IMXDPUV1_ID_SRC_FETCHDECODE3 */
|
||||
IMXDPUV1_CHAN_IDX_19, /* IMXDPUV1_ID_SRC_FETCHDECODE1 */
|
||||
IMXDPUV1_CHAN_IDX_20, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_21, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_22, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_23, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_24, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_25, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_26, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_27, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */
|
||||
IMXDPUV1_CHAN_IDX_28, /* IMXDPUV1_ID_SRC_ECO0 */
|
||||
IMXDPUV1_CHAN_IDX_29, /* IMXDPUV1_ID_SRC_ECO1 */
|
||||
IMXDPUV1_CHAN_IDX_30, /* IMXDPUV1_ID_SRC_ECO2 */
|
||||
IMXDPUV1_CHAN_IDX_IN_MAX, /* Last fetch channel + 1 */
|
||||
|
||||
/* Store Channels */
|
||||
IMXDPUV1_CHAN_IDX_OUT_FIRST = 32,
|
||||
IMXDPUV1_CHAN_IDX_32 = 32,/* IMXDPUV1_ID_DST_STORE4 */
|
||||
IMXDPUV1_CHAN_IDX_33, /* IMXDPUV1_ID_DST_STORE5 */
|
||||
IMXDPUV1_CHAN_IDX_OUT_MAX,/* Last fetch channel + 1 */
|
||||
IMXDPUV1_CHAN_IDX_MAX = IMXDPUV1_CHAN_IDX_OUT_MAX,
|
||||
} imxdpuv1_chan_idx_t;
|
||||
|
||||
typedef enum {
|
||||
IMXDPUV1_SUB_NONE = 0,
|
||||
IMXDPUV1_SUB_1 = 1U << 0, /* IMXDPUV1_ID_FETCHLAYER0, layer 1 */
|
||||
IMXDPUV1_SUB_2 = 1U << 1, /* IMXDPUV1_ID_FETCHLAYER0, layer 2 */
|
||||
IMXDPUV1_SUB_3 = 1U << 2, /* IMXDPUV1_ID_FETCHLAYER0, layer 3 */
|
||||
IMXDPUV1_SUB_4 = 1U << 3, /* IMXDPUV1_ID_FETCHLAYER0, layer 4 */
|
||||
IMXDPUV1_SUB_5 = 1U << 4, /* IMXDPUV1_ID_FETCHLAYER0, layer 5 */
|
||||
IMXDPUV1_SUB_6 = 1U << 5, /* IMXDPUV1_ID_FETCHLAYER0, layer 6 */
|
||||
IMXDPUV1_SUB_7 = 1U << 6, /* IMXDPUV1_ID_FETCHLAYER0, layer 7 */
|
||||
IMXDPUV1_SUB_8 = 1U << 7, /* IMXDPUV1_ID_FETCHLAYER0, layer 8 */
|
||||
} imxdpuv1_chan_sub_idx_t;
|
||||
|
||||
/* IMXDPU Channel
|
||||
* Consistist of four fields
|
||||
* src - block id of source or destination
|
||||
* sec - block id of secondary source for fetcheco
|
||||
* sub - sub index of block for fetchlayer or fetchwarp
|
||||
* idx - logical channel index
|
||||
*
|
||||
*/
|
||||
#define make_channel(__blk_id, __eco_id, __sub, __idx) \
|
||||
(((__u32)(__idx)<<0)|((__u32)(__eco_id)<<8)|((__u32)(__sub)<<16)|((__u32)(__blk_id)<<24))
|
||||
|
||||
#define get_channel_blk(chan) (((__u32)(chan) >> 24) & 0xff)
|
||||
#define get_channel_sub(chan) (((__u32)(chan) >> 16) & 0xff)
|
||||
#define get_eco_idx(chan) (((__u32)(chan) >> 8) & 0xff)
|
||||
#define get_channel_idx(chan) (((__u32)(chan) >> 0) & 0xff)
|
||||
#define IMXDPUV1_SUBCHAN_LAYER_OFFSET 0x28
|
||||
|
||||
typedef enum {
|
||||
#ifdef IMXDPUV1_VERSION_0
|
||||
/* Fetch Channels */
|
||||
IMXDPUV1_CHAN_00 = make_channel(IMXDPUV1_ID_FETCHDECODE2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 0),
|
||||
IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1),
|
||||
IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2),
|
||||
IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3),
|
||||
IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4),
|
||||
IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5),
|
||||
IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6),
|
||||
IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7),
|
||||
IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8),
|
||||
IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9),
|
||||
IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10),
|
||||
IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11),
|
||||
IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12),
|
||||
IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13),
|
||||
IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14),
|
||||
IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15),
|
||||
IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16),
|
||||
IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17),
|
||||
IMXDPUV1_CHAN_18 = make_channel(IMXDPUV1_ID_FETCHDECODE3, 30, IMXDPUV1_SUB_NONE, 18),
|
||||
IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19),
|
||||
IMXDPUV1_CHAN_20 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 20),
|
||||
IMXDPUV1_CHAN_21 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 21),
|
||||
IMXDPUV1_CHAN_22 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 22),
|
||||
IMXDPUV1_CHAN_23 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 23),
|
||||
IMXDPUV1_CHAN_24 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 24),
|
||||
IMXDPUV1_CHAN_25 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 25),
|
||||
IMXDPUV1_CHAN_26 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 26),
|
||||
IMXDPUV1_CHAN_27 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 27),
|
||||
IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28),
|
||||
IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29),
|
||||
IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30),
|
||||
/* Store Channels */
|
||||
IMXDPUV1_CHAN_32 = make_channel(IMXDPUV1_ID_STORE4, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 32),
|
||||
IMXDPUV1_CHAN_33 = make_channel(IMXDPUV1_ID_STORE5, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 33),
|
||||
#else
|
||||
/* Fetch Channels */
|
||||
IMXDPUV1_CHAN_00 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1),
|
||||
IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2),
|
||||
IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3),
|
||||
IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4),
|
||||
IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5),
|
||||
IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6),
|
||||
IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7),
|
||||
IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8),
|
||||
IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9),
|
||||
IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10),
|
||||
IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11),
|
||||
IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12),
|
||||
IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13),
|
||||
IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14),
|
||||
IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15),
|
||||
IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16),
|
||||
IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17),
|
||||
IMXDPUV1_CHAN_18 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19),
|
||||
IMXDPUV1_CHAN_20 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_21 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_22 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_23 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_24 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_25 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_26 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_27 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28),
|
||||
IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29),
|
||||
IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30),
|
||||
/* Store Channels */
|
||||
IMXDPUV1_CHAN_32 = make_channel(0, 0, 0, 0),
|
||||
IMXDPUV1_CHAN_33 = make_channel(0, 0, 0, 0),
|
||||
#endif
|
||||
} imxdpuv1_chan_t;
|
||||
|
||||
/* Aliases for Channels */
|
||||
#define IMXDPUV1_CHAN_VIDEO_0 IMXDPUV1_CHAN_01
|
||||
#define IMXDPUV1_CHAN_VIDEO_1 IMXDPUV1_CHAN_19
|
||||
|
||||
#define IMXDPUV1_CHAN_INTEGRAL_0 IMXDPUV1_CHAN_00
|
||||
#define IMXDPUV1_CHAN_INTEGRAL_1 IMXDPUV1_CHAN_18
|
||||
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_1 IMXDPUV1_CHAN_02
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_2 IMXDPUV1_CHAN_03
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_3 IMXDPUV1_CHAN_04
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_4 IMXDPUV1_CHAN_05
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_5 IMXDPUV1_CHAN_06
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_6 IMXDPUV1_CHAN_07
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_7 IMXDPUV1_CHAN_08
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_0_8 IMXDPUV1_CHAN_09
|
||||
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_1 IMXDPUV1_CHAN_20
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_2 IMXDPUV1_CHAN_21
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_3 IMXDPUV1_CHAN_22
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_4 IMXDPUV1_CHAN_23
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_5 IMXDPUV1_CHAN_24
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_6 IMXDPUV1_CHAN_25
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_7 IMXDPUV1_CHAN_26
|
||||
#define IMXDPUV1_CHAN_FRACTIONAL_1_8 IMXDPUV1_CHAN_27
|
||||
|
||||
#define IMXDPUV1_CHAN_WARP_2_1 IMXDPUV1_CHAN_10
|
||||
#define IMXDPUV1_CHAN_WARP_2_2 IMXDPUV1_CHAN_11
|
||||
#define IMXDPUV1_CHAN_WARP_2_3 IMXDPUV1_CHAN_12
|
||||
#define IMXDPUV1_CHAN_WARP_2_4 IMXDPUV1_CHAN_13
|
||||
#define IMXDPUV1_CHAN_WARP_2_5 IMXDPUV1_CHAN_14
|
||||
#define IMXDPUV1_CHAN_WARP_2_6 IMXDPUV1_CHAN_15
|
||||
#define IMXDPUV1_CHAN_WARP_2_7 IMXDPUV1_CHAN_16
|
||||
#define IMXDPUV1_CHAN_WARP_2_8 IMXDPUV1_CHAN_17
|
||||
|
||||
#define IMXDPUV1_CHAN_CAPTURE_0 IMXDPUV1_CHAN_32
|
||||
#define IMXDPUV1_CHAN_CAPTURE_1 IMXDPUV1_CHAN_33
|
||||
|
||||
|
||||
/* IMXDPU Pixel format definitions */
|
||||
/* Four-character-code (FOURCC) */
|
||||
#ifdef fourcc
|
||||
#warning "fourcc is already defined ... redeifining it here!"
|
||||
#undef fourcc
|
||||
#endif
|
||||
#define fourcc(a, b, c, d)\
|
||||
(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
|
||||
|
||||
|
||||
/*! @} */
|
||||
/*! @name Generic Formats */
|
||||
/*! @{ */
|
||||
#define IMXDPUV1_PIX_FMT_GENERIC fourcc('D', 'P', 'U', '0') /*!< IPU Generic Data */
|
||||
#define IMXDPUV1_PIX_FMT_GENERIC_32 fourcc('D', 'P', 'U', '1') /*!< IPU Generic Data */
|
||||
#define IMXDPUV1_PIX_FMT_GENERIC_16 fourcc('D', 'P', 'U', '2') /*!< IPU Generic Data */
|
||||
|
||||
/*! @} */
|
||||
/*! @name RGB Formats */
|
||||
/*! @{ */
|
||||
#define IMXDPUV1_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
|
||||
#define IMXDPUV1_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
|
||||
#define IMXDPUV1_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 16 RGB-5-6-5 */
|
||||
#define IMXDPUV1_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */
|
||||
#define IMXDPUV1_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */
|
||||
#define IMXDPUV1_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
|
||||
#define IMXDPUV1_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
|
||||
#define IMXDPUV1_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
|
||||
#define IMXDPUV1_PIX_FMT_ARGB32 fourcc('A', 'R', 'G', 'B') /*!< 32 ARGB-8-8-8-8 */
|
||||
|
||||
/*! @} */
|
||||
/*! @name YUV Interleaved Formats */
|
||||
/*! @{ */
|
||||
#define IMXDPUV1_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
|
||||
#define IMXDPUV1_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
|
||||
#define IMXDPUV1_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */
|
||||
#define IMXDPUV1_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */
|
||||
#define IMXDPUV1_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
|
||||
#define IMXDPUV1_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
|
||||
#define IMXDPUV1_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */
|
||||
#define IMXDPUV1_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */
|
||||
|
||||
/* two planes -- one Y, one Cb + Cr interleaved */
|
||||
#define IMXDPUV1_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
|
||||
#define IMXDPUV1_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
|
||||
|
||||
#define IMXDPUV1_CAP_FMT_RGB24 fourcc('R', 'G', 'B', '3')
|
||||
#define IMXDPUV1_CAP_FMT_BT656 fourcc('B', '6', '5', '6')
|
||||
#define IMXDPUV1_CAP_FMT_YUYV fourcc('Y', 'U', 'Y', 'V')
|
||||
|
||||
struct imxdpuv1_soc;
|
||||
/*!
|
||||
* Definition of IMXDPU rectangle structure
|
||||
*/
|
||||
typedef struct {
|
||||
int16_t top; /* y coordinate of top/left pixel */
|
||||
int16_t left; /* x coordinate top/left pixel */
|
||||
int16_t width;
|
||||
int16_t height;
|
||||
} imxdpuv1_rect_t;
|
||||
|
||||
|
||||
/*!
|
||||
* Union of initialization parameters for a logical channel.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
uint8_t blend_mode;
|
||||
uint8_t blend_layer;
|
||||
uint8_t disp_id; /* capture id */
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint32_t const_color;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
} common;
|
||||
struct {
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
uint8_t blend_mode;
|
||||
uint8_t blend_layer;
|
||||
uint8_t capture_id; /* disp_id/capture id */
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint32_t const_color;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
uint32_t h_scale_factor; /* downscaling out/in */
|
||||
uint32_t h_phase;
|
||||
uint32_t v_scale_factor; /* downscaling out/in */
|
||||
uint32_t v_phase[2][2];
|
||||
bool use_video_proc;
|
||||
bool interlaced;
|
||||
} store;
|
||||
struct {
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
uint8_t blend_mode;
|
||||
uint8_t blend_layer;
|
||||
uint8_t disp_id;
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint32_t const_color;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
uint32_t h_scale_factor; /* downscaling out/in */
|
||||
uint32_t h_phase;
|
||||
uint32_t v_scale_factor; /* downscaling out/in */
|
||||
uint32_t v_phase[2][2];
|
||||
bool use_video_proc;
|
||||
bool interlaced;
|
||||
} fetch_decode;
|
||||
struct {
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
uint8_t blend_mode;
|
||||
uint8_t blend_layer;
|
||||
uint8_t disp_id; /* capture id */
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint32_t const_color;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
} fetch_layer;
|
||||
struct {
|
||||
imxdpuv1_chan_t chan;
|
||||
uint32_t src_pixel_fmt;
|
||||
uint16_t src_width;
|
||||
uint16_t src_height;
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
uint16_t stride;
|
||||
uint32_t dest_pixel_fmt;
|
||||
uint8_t blend_mode;
|
||||
uint8_t blend_layer;
|
||||
uint8_t disp_id; /* capture id */
|
||||
int16_t dest_top;
|
||||
int16_t dest_left;
|
||||
uint16_t dest_width;
|
||||
uint16_t dest_height;
|
||||
uint32_t const_color;
|
||||
bool use_global_alpha;
|
||||
bool use_local_alpha;
|
||||
} fetch_warp;
|
||||
} imxdpuv1_channel_params_t;
|
||||
|
||||
/*!
|
||||
* Enumeration of IMXDPU video mode flags
|
||||
*/
|
||||
enum imxdpuv1_mode_flags {
|
||||
/* 1 is active high 0 is active low */
|
||||
IMXDPUV1_MODE_FLAGS_HSYNC_POL = 1 << 0,
|
||||
IMXDPUV1_MODE_FLAGS_VSYNC_POL = 1 << 1,
|
||||
IMXDPUV1_MODE_FLAGS_DE_POL = 1 << 2,
|
||||
|
||||
/* drive data on positive .edge */
|
||||
IMXDPUV1_MODE_FLAGS_CLK_POL = 1 << 3,
|
||||
|
||||
IMXDPUV1_MODE_FLAGS_INTERLACED = 1 << 4 ,
|
||||
|
||||
/* Left/Right Synchronous display mode, both display pipe are
|
||||
combined to make one display. All mode timings are divided by
|
||||
two for each half screen.
|
||||
Note: This may not be needed we may force this for any width
|
||||
over ~2048
|
||||
*/
|
||||
IMXDPUV1_MODE_FLAGS_LRSYNC = 1 << 8,
|
||||
|
||||
/* Split mode each pipe is split into two displays */
|
||||
IMXDPUV1_MODE_FLAGS_SPLIT = 1 << 9,
|
||||
|
||||
IMXDPUV1_MODE_FLAGS_32BIT = 1 << 16,
|
||||
IMXDPUV1_MODE_FLAGS_BT656_10BIT = 1 << 17,
|
||||
IMXDPUV1_MODE_FLAGS_BT656_8BIT = 1 << 18,
|
||||
};
|
||||
|
||||
struct imxdpuv1_videomode {
|
||||
char name[64]; /* may not be needed */
|
||||
|
||||
uint32_t pixelclock; /* Hz */
|
||||
|
||||
/* htotal (pixels) = hlen + hfp + hsync + hbp */
|
||||
uint32_t hlen;
|
||||
uint32_t hfp;
|
||||
uint32_t hbp;
|
||||
uint32_t hsync;
|
||||
|
||||
/* field0 - vtotal (lines) = vlen + vfp + vsync + vbp */
|
||||
uint32_t vlen;
|
||||
uint32_t vfp;
|
||||
uint32_t vbp;
|
||||
uint32_t vsync;
|
||||
|
||||
/* field1 */
|
||||
uint32_t vlen1;
|
||||
uint32_t vfp1;
|
||||
uint32_t vbp1;
|
||||
uint32_t vsync1;
|
||||
|
||||
uint32_t flags;
|
||||
uint32_t format;
|
||||
uint32_t dest_format; /*buffer format for capture*/
|
||||
int16_t clip_top;
|
||||
int16_t clip_left;
|
||||
uint16_t clip_width;
|
||||
uint16_t clip_height;
|
||||
|
||||
};
|
||||
|
||||
#define IMXDPUV1_ENABLE 1
|
||||
#define IMXDPUV1_DISABLE 0
|
||||
|
||||
#define IMXDPUV1_TRUE 1
|
||||
#define IMXDPUV1_FALSE 0
|
||||
#define IMXDPUV1_OFFSET_INVALID 0x10000000 /* this should force an access error */
|
||||
#define IMXDPUV1_CHANNEL_INVALID 0x0 /* this should force an access error */
|
||||
|
||||
#define IMXDPUV1_MIN(_X, _Y) ((_X) < (_Y) ? (_X) : (_Y))
|
||||
|
||||
/* Native color type */
|
||||
#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU
|
||||
#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U
|
||||
#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U
|
||||
#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U
|
||||
#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U
|
||||
#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U
|
||||
#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U
|
||||
#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U
|
||||
|
||||
#define IMXDPUV1_IRQF_NONE 0x0
|
||||
#define IMXDPUV1_IRQF_ONESHOT 0x1
|
||||
#define IMXDPUV1_INTERRUPT_MAX (66 + 1) /* IMXDPUV1_FRAMECAP5_SYNC_OFF_IRQ
|
||||
(66) is last interrupt */
|
||||
|
||||
int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq);
|
||||
int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq);
|
||||
int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq);
|
||||
int imxdpuv1_init_irqs(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_request_irq(int8_t imxdpuv1_id,
|
||||
uint32_t irq,
|
||||
int(*handler) (int, void *),
|
||||
uint32_t irq_flags,
|
||||
const char *devname, void *data) ;
|
||||
int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data);
|
||||
int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_handle_irq(int32_t imxdpuv1_id);
|
||||
struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_init(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, int8_t disp,
|
||||
uint32_t pixel_fmt,
|
||||
struct imxdpuv1_videomode mode);
|
||||
int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp);
|
||||
int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp);
|
||||
int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp);
|
||||
int imxdpuv1_disp_setup_frame_gen(
|
||||
int8_t imxdpuv1_id,
|
||||
int8_t disp,
|
||||
const struct imxdpuv1_videomode *mode,
|
||||
uint16_t cc_red, /* 10 bits */
|
||||
uint16_t cc_green, /* 10 bits */
|
||||
uint16_t cc_blue, /* 10 bits */
|
||||
uint8_t cc_alpha,
|
||||
bool test_mode_enable);
|
||||
int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id,
|
||||
int8_t disp,
|
||||
bool enable);
|
||||
int imxdpuv1_disp_setup_constframe(int8_t imxdpuv1_id,
|
||||
int8_t disp,
|
||||
uint8_t bg_red,
|
||||
uint8_t bg_green,
|
||||
uint8_t bg_blue,
|
||||
uint8_t bg_alpha);
|
||||
int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id,
|
||||
const imxdpuv1_layer_t *layer,
|
||||
imxdpuv1_layer_idx_t layer_idx,
|
||||
bool is_top_layer);
|
||||
void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode);
|
||||
int imxdpuv1_bytes_per_pixel(uint32_t fmt);
|
||||
int imxdpuv1_init_channel_buffer(int8_t imxdpuv1_id,
|
||||
imxdpuv1_chan_t chan,
|
||||
uint32_t stride,
|
||||
imxdpuv1_rotate_mode_t rot_mode,
|
||||
dma_addr_t phyaddr_0,
|
||||
uint32_t u_offset,
|
||||
uint32_t v_offset);
|
||||
int32_t imxdpuv1_update_channel_buffer(int8_t imxdpuv1_id,
|
||||
imxdpuv1_chan_t chan,
|
||||
dma_addr_t phyaddr_0);
|
||||
int imxdpuv1_init_channel(int8_t imxdpuv1_id,
|
||||
imxdpuv1_channel_params_t *params);
|
||||
int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id,
|
||||
imxdpuv1_layer_idx_t layer_idx,
|
||||
uint8_t alpha);
|
||||
int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id,
|
||||
imxdpuv1_layer_idx_t layer_idx,
|
||||
int16_t x, int16_t y);
|
||||
int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id,
|
||||
imxdpuv1_chan_t chan,
|
||||
int16_t x, int16_t y);
|
||||
int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp);
|
||||
int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id);
|
||||
void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id);
|
||||
void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id,
|
||||
int8_t disp,
|
||||
uint64_t mask);
|
||||
int imxdpuv1_disp_set_chan_crop(int8_t imxdpuv1_id,
|
||||
imxdpuv1_chan_t chan,
|
||||
int16_t clip_top,
|
||||
int16_t clip_left,
|
||||
uint16_t clip_width,
|
||||
uint16_t clip_height,
|
||||
int16_t dest_top,
|
||||
int16_t dest_left,
|
||||
uint16_t dest_width,
|
||||
uint16_t dest_height);
|
||||
void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id);
|
||||
int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan);
|
||||
uint32_t imxdpuv1_get_planes(uint32_t fmt);
|
||||
|
||||
int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id,
|
||||
imxdpuv1_chan_t chan,
|
||||
uint32_t src_pixel_fmt,
|
||||
uint16_t src_width,
|
||||
uint16_t src_height,
|
||||
int16_t clip_top,
|
||||
int16_t clip_left,
|
||||
uint16_t clip_width,
|
||||
uint16_t clip_height,
|
||||
uint16_t stride,
|
||||
uint8_t disp_id,
|
||||
int16_t dest_top,
|
||||
int16_t dest_left,
|
||||
uint16_t dest_width,
|
||||
uint16_t dest_height,
|
||||
uint32_t const_color,
|
||||
bool use_global_alpha,
|
||||
bool use_local_alpha,
|
||||
unsigned int disp_addr);
|
||||
int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp);
|
||||
|
||||
int imxdpuv1_cap_setup_frame(
|
||||
int8_t imxdpuv1_id,
|
||||
int8_t src_id,
|
||||
int8_t dest_id,
|
||||
int8_t sync_count,
|
||||
const struct imxdpuv1_videomode *cap_mode);
|
||||
int imxdpuv1_cap_setup_crop(
|
||||
int8_t imxdpuv1_id,
|
||||
int8_t src_id,
|
||||
int16_t clip_top,
|
||||
int16_t clip_left,
|
||||
uint16_t clip_width,
|
||||
uint16_t clip_height);
|
||||
|
||||
int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable);
|
||||
int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask);
|
||||
|
||||
/* FIXME: add api if needed */
|
||||
static inline int32_t imxdpuv1_csi_enable_mclk_if(int8_t imxdpuv1_id, int src, uint32_t cap,
|
||||
bool flag, bool wait)
|
||||
{
|
||||
printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__);
|
||||
return 0;
|
||||
}
|
||||
#endif /* IMXDPUV1_H */
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
/*
|
||||
* Copyright (c) 2005-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef IMXDPUV1_EVENTS_H
|
||||
#define IMXDPUV1_EVENTS_H
|
||||
|
||||
/* Shadow load (Blit Engine) */
|
||||
#define IMXDPUV1_STORE9_SHDLOAD_IRQ 0U
|
||||
#define IMXDPUV1_STORE9_SHDLOAD_CMD 0U
|
||||
|
||||
/* Frame complete (Blit Engine) */
|
||||
#define IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ 1U
|
||||
#define IMXDPUV1_STORE9_FRAMECOMPLETE_CMD 1U
|
||||
|
||||
/* Sequence complete (Blit Engine) */
|
||||
#define IMXDPUV1_STORE9_SEQCOMPLETE_IRQ 2U
|
||||
#define IMXDPUV1_STORE9_SEQCOMPLETE_CMD 2U
|
||||
|
||||
/* Shadow load (Display Controller Content Stream 0) */
|
||||
#define IMXDPUV1_EXTDST0_SHDLOAD_IRQ 3U
|
||||
#define IMXDPUV1_EXTDST0_SHDLOAD_CMD 3U
|
||||
|
||||
/* Frame complete (Display Controller Content Stream 0) */
|
||||
#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ 4U
|
||||
#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_CMD 4U
|
||||
|
||||
/* Sequence complete (Display Controller Content Stream 0) */
|
||||
#define IMXDPUV1_EXTDST0_SEQCOMPLETE_IRQ 5U
|
||||
#define IMXDPUV1_EXTDST0_SEQCOMPLETE_CMD 5U
|
||||
|
||||
/* Shadow load (Display Controller Safety Stream 0) */
|
||||
#define IMXDPUV1_EXTDST4_SHDLOAD_IRQ 6U
|
||||
#define IMXDPUV1_EXTDST4_SHDLOAD_CMD 6U
|
||||
|
||||
/* Frame complete (Display Controller Safety Stream 0) */
|
||||
#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_IRQ 7U
|
||||
#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_CMD 7U
|
||||
|
||||
/* Sequence complete (Display Controller Safety Stream 0) */
|
||||
#define IMXDPUV1_EXTDST4_SEQCOMPLETE_IRQ 8U
|
||||
#define IMXDPUV1_EXTDST4_SEQCOMPLETE_CMD 8U
|
||||
|
||||
/* Shadow load (Display Controller Content Stream 1) */
|
||||
#define IMXDPUV1_EXTDST1_SHDLOAD_IRQ 9U
|
||||
#define IMXDPUV1_EXTDST1_SHDLOAD_CMD 9U
|
||||
|
||||
/* Frame complete (Display Controller Content Stream 1) */
|
||||
#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ 10U
|
||||
#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_CMD 10U
|
||||
|
||||
/* Sequence complete (Display Controller Content Stream 1) */
|
||||
#define IMXDPUV1_EXTDST1_SEQCOMPLETE_IRQ 11U
|
||||
#define IMXDPUV1_EXTDST1_SEQCOMPLETE_CMD 11U
|
||||
|
||||
/* Shadow load (Display Controller Safety Stream 1) */
|
||||
#define IMXDPUV1_EXTDST5_SHDLOAD_IRQ 12U
|
||||
#define IMXDPUV1_EXTDST5_SHDLOAD_CMD 12U
|
||||
|
||||
/* Frame complete (Display Controller Safety Stream 1) */
|
||||
#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_IRQ 13U
|
||||
#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_CMD 13U
|
||||
|
||||
/* Sequence complete (Display Controller Safety Stream 1) */
|
||||
#define IMXDPUV1_EXTDST5_SEQCOMPLETE_IRQ 14U
|
||||
#define IMXDPUV1_EXTDST5_SEQCOMPLETE_CMD 14U
|
||||
|
||||
/* Shadow load (Display Controller Display Stream 0) */
|
||||
#define IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ 15U
|
||||
#define IMXDPUV1_DISENGCFG_SHDLOAD0_CMD 15U
|
||||
|
||||
/* Frame complete (Display Controller Display Stream 0) */
|
||||
#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ 16U
|
||||
#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_CMD 16U
|
||||
|
||||
/* Sequence complete (Display Controller Display Stream 0) */
|
||||
#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_IRQ 17U
|
||||
#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_CMD 17U
|
||||
|
||||
/* Programmable interrupt 0 (Display Controller Display Stream 0 FrameGen #0 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN0_INT0_IRQ 18U
|
||||
#define IMXDPUV1_FRAMEGEN0_INT0_CMD 18U
|
||||
|
||||
/* Programmable interrupt 1 (Display Controller Display Stream 0 FrameGen #0 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN0_INT1_IRQ 19U
|
||||
#define IMXDPUV1_FRAMEGEN0_INT1_CMD 19U
|
||||
|
||||
/* Programmable interrupt 2 (Display Controller Display Stream 0 FrameGen #0 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN0_INT2_IRQ 20U
|
||||
#define IMXDPUV1_FRAMEGEN0_INT2_CMD 20U
|
||||
|
||||
/* Programmable interrupt 3 (Display Controller Display Stream 0 FrameGen #0 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN0_INT3_IRQ 21U
|
||||
#define IMXDPUV1_FRAMEGEN0_INT3_CMD 21U
|
||||
|
||||
/* Shadow load (Display Controller Display Stream 0 Sig #0 unit) */
|
||||
#define IMXDPUV1_SIG0_SHDLOAD_IRQ 22U
|
||||
#define IMXDPUV1_SIG0_SHDLOAD_CMD 22U
|
||||
|
||||
/* Measurement valid (Display Controller Display Stream 0 Sig #0 unit) */
|
||||
#define IMXDPUV1_SIG0_VALID_IRQ 23U
|
||||
#define IMXDPUV1_SIG0_VALID_CMD 23U
|
||||
|
||||
/* Error condition (Display Controller Display Stream 0 Sig #0 unit) */
|
||||
#define IMXDPUV1_SIG0_ERROR_IRQ 24U
|
||||
#define IMXDPUV1_SIG0_ERROR_CMD 24U
|
||||
|
||||
/* Shadow load (Display Controller Display Stream 1) */
|
||||
#define IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ 25U
|
||||
#define IMXDPUV1_DISENGCFG_SHDLOAD1_CMD 25U
|
||||
|
||||
/* Frame complete (Display Controller Display Stream 1) */
|
||||
#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_IRQ 26U
|
||||
#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_CMD 26U
|
||||
|
||||
/* Sequence complete (Display Controller Display Stream 1) */
|
||||
#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_IRQ 27U
|
||||
#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_CMD 27U
|
||||
|
||||
/* Programmable interrupt 0 (Display Controller Display Stream 1 FrameGen #1 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN1_INT0_IRQ 28U
|
||||
#define IMXDPUV1_FRAMEGEN1_INT0_CMD 28U
|
||||
|
||||
/* Programmable interrupt 1 (Display Controller Display Stream 1 FrameGen #1 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN1_INT1_IRQ 29U
|
||||
#define IMXDPUV1_FRAMEGEN1_INT1_CMD 29U
|
||||
|
||||
/* Programmable interrupt 2 (Display Controller Display Stream 1 FrameGen #1 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN1_INT2_IRQ 30U
|
||||
#define IMXDPUV1_FRAMEGEN1_INT2_CMD 30U
|
||||
|
||||
/* Programmable interrupt 3 (Display Controller Display Stream 1 FrameGen #1 unit) */
|
||||
#define IMXDPUV1_FRAMEGEN1_INT3_IRQ 31U
|
||||
#define IMXDPUV1_FRAMEGEN1_INT3_CMD 31U
|
||||
|
||||
/* Shadow load (Display Controller Display Stream 1 Sig #1 unit) */
|
||||
#define IMXDPUV1_SIG1_SHDLOAD_IRQ 32U
|
||||
#define IMXDPUV1_SIG1_SHDLOAD_CMD 32U
|
||||
|
||||
/* Measurement valid (Display Controller Display Stream 1 Sig #1 unit) */
|
||||
#define IMXDPUV1_SIG1_VALID_IRQ 33U
|
||||
#define IMXDPUV1_SIG1_VALID_CMD 33U
|
||||
|
||||
/* Error condition (Display Controller Display Stream 1 Sig #1 unit) */
|
||||
#define IMXDPUV1_SIG1_ERROR_IRQ 34U
|
||||
#define IMXDPUV1_SIG1_ERROR_CMD 34U
|
||||
|
||||
/* Reserved Do not use */
|
||||
#define IMXDPUV1_RESERVED35_IRQ 35U
|
||||
#define IMXDPUV1_RESERVED35_CMD 35U
|
||||
|
||||
/* Error condition (Command Sequencer) */
|
||||
#define IMXDPUV1_CMDSEQ_ERROR_IRQ 36U
|
||||
#define IMXDPUV1_CMDSEQ_ERROR_CMD 36U
|
||||
|
||||
/* Software interrupt 0 (Common Control) */
|
||||
#define IMXDPUV1_COMCTRL_SW0_IRQ 37U
|
||||
#define IMXDPUV1_COMCTRL_SW0_CMD 37U
|
||||
|
||||
/* Software interrupt 1 (Common Control) */
|
||||
#define IMXDPUV1_COMCTRL_SW1_IRQ 38U
|
||||
#define IMXDPUV1_COMCTRL_SW1_CMD 38U
|
||||
|
||||
/* Software interrupt 2 (Common Control) */
|
||||
#define IMXDPUV1_COMCTRL_SW2_IRQ 39U
|
||||
#define IMXDPUV1_COMCTRL_SW2_CMD 39U
|
||||
|
||||
/* Software interrupt 3 (Common Control) */
|
||||
#define IMXDPUV1_COMCTRL_SW3_IRQ 40U
|
||||
#define IMXDPUV1_COMCTRL_SW3_CMD 40U
|
||||
|
||||
/* Synchronization status activated (Display Controller Safety stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_IRQ 41U
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_CMD 41U
|
||||
|
||||
/* Synchronization status deactivated (Display Controller Safety stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_IRQ 42U
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_CMD 42U
|
||||
|
||||
/* Synchronization status activated (Display Controller Content stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_IRQ 43U
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_CMD 43U
|
||||
|
||||
/* Synchronization status deactivated (Display Controller Content stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_IRQ 44U
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_CMD 44U
|
||||
|
||||
/* Synchronization status activated (Display Controller Safety stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_IRQ 45U
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_CMD 45U
|
||||
|
||||
/* Synchronization status deactivated (Display Controller Safety stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_IRQ 46U
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_CMD 46U
|
||||
|
||||
/* Synchronization status activated (Display Controller Content stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_IRQ 47U
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_CMD 47U
|
||||
|
||||
/* Synchronization status deactivated (Display Controller Content stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_IRQ 48U
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_CMD 48U
|
||||
|
||||
/* Synchronization status (Display Controller Safety stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_CMD 49U
|
||||
#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_STS 0U
|
||||
|
||||
/* Synchronization status (Display Controller Content stream 0) */
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_CMD 50U
|
||||
#define IMXDPUV1_FRAMEGEN0_SECSYNC_STS 1U
|
||||
|
||||
/* Synchronization status (Display Controller Safety stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_CMD 51U
|
||||
#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_STS 2U
|
||||
|
||||
/* Synchronization status (Display Controller Content stream 1) */
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_CMD 52U
|
||||
#define IMXDPUV1_FRAMEGEN1_SECSYNC_STS 3U
|
||||
|
||||
/* Shadow load request (Display Controller Pixel Engine configuration Store #9 synchronizer) */
|
||||
#define IMXDPUV1_PIXENGCFG_STORE9_SHDLDREQ_CMD 53U
|
||||
|
||||
/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #0 synchronizer) */
|
||||
#define IMXDPUV1_PIXENGCFG_EXTDST0_SHDLDREQ_CMD 54U
|
||||
|
||||
/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #4 synchronizer) */
|
||||
#define IMXDPUV1_PIXENGCFG_EXTDST4_SHDLDREQ_CMD 55U
|
||||
|
||||
/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #1 synchronizer) */
|
||||
#define IMXDPUV1_PIXENGCFG_EXTDST1_SHDLDREQ_CMD 56U
|
||||
|
||||
/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #5 synchronizer) */
|
||||
#define IMXDPUV1_PIXENGCFG_EXTDST5_SHDLDREQ_CMD 57U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchDecode #9 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_SHDLDREQ_CMD 58U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHWARP9_SHDLDREQ_CMD 59U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchEco #9 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHECO9_SHDLDREQ_CMD 60U
|
||||
|
||||
/* Shadow load request (Display Controller ConstFrame #0 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_SHDLDREQ_CMD 61U
|
||||
|
||||
/* Shadow load request (Display Controller ConstFrame #4 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_SHDLDREQ_CMD 62U
|
||||
|
||||
/* Shadow load request (Display Controller ConstFrame #1 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_SHDLDREQ_CMD 63U
|
||||
|
||||
/* Shadow load request (Display Controller ConstFrame #5 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_SHDLDREQ_CMD 64U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHWARP2_SHDLDREQ_CMD 65U
|
||||
|
||||
/* Shadow load request (Display Controller FetchEco #2 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHECO2_SHDLDREQ_CMD 66U
|
||||
|
||||
/* Shadow load request (Display Controller FetchDecode #0 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_SHDLDREQ_CMD 67U
|
||||
|
||||
/* Shadow load request (Display Controller FetchEco #0 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHECO0_SHDLDREQ_CMD 68U
|
||||
|
||||
/* Shadow load request (Display Controller FetchDecode #1 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_SHDLDREQ_CMD 69U
|
||||
|
||||
/* Shadow load request (Display Controller FetchEco #1 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHECO1_SHDLDREQ_CMD 70U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 tree) */
|
||||
#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_SHDLDREQ_CMD 71U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 0) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ0_CMD 72U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 1) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ1_CMD 73U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 2) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ2_CMD 74U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 3) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ3_CMD 75U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 4) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ4_CMD 76U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 5) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ5_CMD 77U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 6) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ6_CMD 78U
|
||||
|
||||
/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 7) */
|
||||
#define IMXDPUV1_FETCHWARP9_SHDLDREQ7_CMD 79U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 0) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ0_CMD 80U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 1) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ1_CMD 81U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 2) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ2_CMD 82U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 3) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ3_CMD 83U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 4) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ4_CMD 84U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 5) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ5_CMD 85U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 6) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ6_CMD 86U
|
||||
|
||||
/* Shadow load request (Display Controller FetchWarp #2 unit Layer 7) */
|
||||
#define IMXDPUV1_FETCHWARP2_SHDLDREQ7_CMD 87U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 0) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ0_CMD 88U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 1) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ1_CMD 89U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 2) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ2_CMD 90U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 3) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ3_CMD 91U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 4) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ4_CMD 92U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 5) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ5_CMD 93U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 6) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ6_CMD 94U
|
||||
|
||||
/* Shadow load request (Display Controller FetchLayer #0 unit Layer 7) */
|
||||
#define IMXDPUV1_FETCHLAYER0_SHDLDREQ7_CMD 95U
|
||||
|
||||
|
||||
#endif /* IMXDPUV1_EVENTS */
|
||||
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Reference in New Issue