MLK-18591-11 android: iot: Add board support imx7d multa
Add imx7d multa board support for android things Signed-off-by: fang hui <hui.fang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
parent
02ad0349e4
commit
1b60a63576
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@ -76,6 +76,13 @@ config TARGET_PICO_IMX7D
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select DM
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select DM_THERMAL
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config TARGET_MULTA_IMX7D
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bool "Support multa-imx7d"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_WARP7
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bool "warp7"
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select BOARD_LATE_INIT
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@ -101,6 +108,7 @@ source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
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source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
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source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
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source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
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source "board/freescale/multa-imx7d/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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@ -0,0 +1,12 @@
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if TARGET_MULTA_IMX7D
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config SYS_BOARD
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default "multa-imx7d"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "multa-imx7d"
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endif
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@ -0,0 +1,6 @@
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MULTA IMX7D BOARD
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M: Fang Hui <hui.fang@nxp.com>
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S: Maintained
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F: board/freescale/multa-imx7d
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F: include/configs/multa-imx7d.h
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F: configs/multa-imx7d_defconfig
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@ -0,0 +1,6 @@
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# Copyright 2017 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := multa-imx7d.o
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@ -0,0 +1,116 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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#ifdef CONFIG_SYS_BOOT_QSPI
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BOOT_FROM qspi
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#elif defined(CONFIG_SYS_BOOT_EIMNOR)
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BOOT_FROM nor
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#else
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BOOT_FROM sd
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#endif
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/multa-imx7d/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x09081109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a0200 0x00000016
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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DATA 4 0x30391000 0x00000000
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000b24
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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CHECK_BITS_SET 4 0x307900c4 0x1
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,227 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/* DDR script */
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.macro imx7d_ddrphy_latency_setting
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ldr r2, =ANATOP_BASE_ADDR
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ldr r3, [r2, #0x800]
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and r3, r3, #0xFF
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cmp r3, #0x11
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bne NO_DELAY
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/*TO 1.1*/
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ldr r1, =0x00000dee
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str r1, [r0, #0x9c]
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ldr r1, =0x18181818
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str r1, [r0, #0x7c]
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ldr r1, =0x18181818
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str r1, [r0, #0x80]
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ldr r1, =0x40401818
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str r1, [r0, #0x84]
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ldr r1, =0x00000040
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str r1, [r0, #0x88]
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ldr r1, =0x40404040
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str r1, [r0, #0x6c]
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b TUNE_END
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NO_DELAY:
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/*TO 1.0*/
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ldr r1, =0x00000b24
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str r1, [r0, #0x9c]
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TUNE_END:
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.endm
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.macro imx7d_ddr_freq_setting
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ldr r2, =ANATOP_BASE_ADDR
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ldr r3, [r2, #0x800]
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and r3, r3, #0xFF
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cmp r3, #0x11
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bne FREQ_DEFAULT_533
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/* Change to 400Mhz for TO1.1 */
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ldr r0, =ANATOP_BASE_ADDR
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ldr r1, =0x70
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ldr r2, =0x00703021
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str r2, [r0, r1]
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ldr r1, =0x90
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ldr r2, =0x0
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str r2, [r0, r1]
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ldr r1, =0x70
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ldr r2, =0x00603021
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str r2, [r0, r1]
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ldr r3, =0x80000000
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wait_lock:
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ldr r2, [r0, r1]
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and r2, r3
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cmp r2, r3
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bne wait_lock
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x9880
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ldr r2, =0x1
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str r2, [r0, r1]
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FREQ_DEFAULT_533:
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.endm
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.macro imx7d_multa_ddr_setting
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imx7d_ddr_freq_setting
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/* Configure ocram_epdc */
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ldr r0, =IOMUXC_GPR_BASE_ADDR
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ldr r1, =0x4f400005
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str r1, [r0, #0x4]
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/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
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ldr r0, =ANATOP_BASE_ADDR
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ldr r1, =(0x1 << 30)
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str r1, [r0, #0x388]
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str r1, [r0, #0x384]
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ldr r0, =SRC_BASE_ADDR
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ldr r1, =0x2
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ldr r2, =0x1000
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str r1, [r0, r2]
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ldr r0, =DDRC_IPS_BASE_ADDR
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ldr r1, =0x01040001
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str r1, [r0]
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ldr r1, =0x80400003
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str r1, [r0, #0x1a0]
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ldr r1, =0x00100020
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str r1, [r0, #0x1a4]
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ldr r1, =0x80100004
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str r1, [r0, #0x1a8]
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ldr r1, =0x00400046
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str r1, [r0, #0x64]
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ldr r1, =0x1
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str r1, [r0, #0x490]
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ldr r1, =0x00020001
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str r1, [r0, #0xd0]
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ldr r1, =0x00690000
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str r1, [r0, #0xd4]
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ldr r1, =0x09300004
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str r1, [r0, #0xdc]
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ldr r1, =0x04080000
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str r1, [r0, #0xe0]
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ldr r1, =0x00100004
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str r1, [r0, #0xe4]
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ldr r1, =0x33f
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str r1, [r0, #0xf4]
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ldr r1, =0x09081109
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str r1, [r0, #0x100]
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ldr r1, =0x0007020d
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str r1, [r0, #0x104]
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ldr r1, =0x03040407
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str r1, [r0, #0x108]
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ldr r1, =0x00002006
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str r1, [r0, #0x10c]
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ldr r1, =0x04020205
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str r1, [r0, #0x110]
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ldr r1, =0x03030202
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str r1, [r0, #0x114]
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ldr r1, =0x00000803
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str r1, [r0, #0x120]
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ldr r1, =0x00800020
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str r1, [r0, #0x180]
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ldr r1, =0x02000100
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str r1, [r0, #0x184]
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ldr r1, =0x02098204
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str r1, [r0, #0x190]
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ldr r1, =0x00030303
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str r1, [r0, #0x194]
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ldr r1, =0x00000016
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str r1, [r0, #0x200]
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ldr r1, =0x00080808
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str r1, [r0, #0x204]
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ldr r1, =0x00000f0f
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str r1, [r0, #0x210]
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ldr r1, =0x07070707
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str r1, [r0, #0x214]
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ldr r1, =0x0f070707
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str r1, [r0, #0x218]
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ldr r1, =0x06000604
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str r1, [r0, #0x240]
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ldr r1, =0x00000001
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str r1, [r0, #0x244]
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ldr r0, =SRC_BASE_ADDR
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mov r1, #0x0
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ldr r2, =0x1000
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str r1, [r0, r2]
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ldr r0, =DDRPHY_IPS_BASE_ADDR
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ldr r1, =0x17420f40
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str r1, [r0]
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ldr r1, =0x10210100
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str r1, [r0, #0x4]
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ldr r1, =0x00060807
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str r1, [r0, #0x10]
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ldr r1, =0x1010007e
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str r1, [r0, #0xb0]
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imx7d_ddrphy_latency_setting
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ldr r1, =0x08080808
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str r1, [r0, #0x20]
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ldr r1, =0x08080808
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str r1, [r0, #0x30]
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ldr r1, =0x01000010
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str r1, [r0, #0x50]
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ldr r1, =0x0e407304
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str r1, [r0, #0xc0]
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ldr r1, =0x0e447304
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str r1, [r0, #0xc0]
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ldr r1, =0x0e447306
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str r1, [r0, #0xc0]
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wait_zq:
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ldr r1, [r0, #0xc4]
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tst r1, #0x1
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beq wait_zq
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ldr r1, =0x0e407304
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str r1, [r0, #0xc0]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0x0
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ldr r2, =0x4130
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str r1, [r0, r2]
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ldr r0, =IOMUXC_GPR_BASE_ADDR
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mov r1, #0x178
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str r1, [r0, #0x20]
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ldr r0, =CCM_BASE_ADDR
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mov r1, #0x2
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ldr r2, =0x4130
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str r1, [r0, r2]
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ldr r0, =DDRPHY_IPS_BASE_ADDR
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ldr r1, =0x0000000f
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str r1, [r0, #0x18]
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ldr r0, =DDRC_IPS_BASE_ADDR
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wait_stat:
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ldr r1, [r0, #0x4]
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tst r1, #0x1
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beq wait_stat
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.endm
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.macro imx7_clock_gating
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.endm
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.macro imx7_qos_setting
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.endm
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.macro imx7_ddr_setting
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imx7d_multa_ddr_setting
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.endm
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/* include the common plugin code here */
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#include <asm/arch/mx7_plugin.S>
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@ -0,0 +1,35 @@
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/multa-imx7d/imximage.cfg,ANDROID_THINGS_SUPPORT"
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CONFIG_ARM=y
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CONFIG_ARCH_MX7=y
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CONFIG_SYS_TEXT_BASE=0x87800000
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CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
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CONFIG_TARGET_MULTA_IMX7D=y
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CONFIG_BOOTDELAY=3
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CONFIG_EFI_PARTITION=y
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ANDROID_BOOT_IMAGE=y
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CONFIG_VIDEO=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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CONFIG_OF_LIBFDT=y
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@ -0,0 +1,345 @@
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/*
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* Copyright 2017 NXP
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*
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* Configuration settings for the Freescale i.MX7D MULTA board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MULTA_IMX7D__CONFIG_H
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#define __MULTA_IMX7D__CONFIG_H
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#include "mx7_common.h"
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|
||||
#define PHYS_SDRAM_SIZE SZ_512M
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define CONFIG_FEC_ENET_DEV 1
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x0
|
||||
|
||||
#if (CONFIG_FEC_ENET_DEV == 0)
|
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
||||
#elif (CONFIG_FEC_ENET_DEV == 1)
|
||||
#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET2_IPS_BASE_ADDR
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_AXP152_POWER
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 3
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#ifdef CONFIG_IMX_BOOTAUX
|
||||
/* Set to QSPI1 A flash at default */
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */
|
||||
#else
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
|
||||
"update_m4_from_sd=" \
|
||||
"if sf probe 0:0; then " \
|
||||
"if run loadm4image; then " \
|
||||
"setexpr fw_sz ${filesize} + 0xffff; " \
|
||||
"setexpr fw_sz ${fw_sz} / 0x10000; " \
|
||||
"setexpr fw_sz ${fw_sz} * 0x10000; " \
|
||||
"sf erase 0x100000 ${fw_sz}; " \
|
||||
"sf write ${loadaddr} 0x100000 ${filesize}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#else
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \
|
||||
"m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#endif
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#define CONFIG_DFU_ENV_SETTINGS \
|
||||
"dfu_alt_info=image raw 0 0x800000;"\
|
||||
"u-boot raw 0 0x4000;"\
|
||||
"bootimg part 0 1;"\
|
||||
"rootfs part 0 2\0" \
|
||||
|
||||
#if defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"panel=TFT43AB\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"bootargs=console=ttymxc0,115200 ubi.mtd=4 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
UPDATE_M4_ENV \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
CONFIG_DFU_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7d-sdb.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"panel=TFT43AB\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
/*
|
||||
* If want to use nand, define CONFIG_NAND_MXS and rework board
|
||||
* to support nand, since emmc has pin conflicts with nand
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_QSPI_BASE QSPI1_IPS_BASE_ADDR
|
||||
#define CONFIG_QSPI_MEMMAP_BASE QSPI0_ARB_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET (60 << 20)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#endif
|
||||
|
||||
/* MMC Config*/
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_USB_EHCI_MX7
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
|
||||
/* #define CONFIG_SPLASH_SCREEN*/
|
||||
/* #define CONFIG_MXC_EPDC*/
|
||||
|
||||
/*
|
||||
* SPLASH SCREEN Configs
|
||||
*/
|
||||
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
|
||||
/*
|
||||
* Framebuffer and LCD
|
||||
*/
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
#undef LCD_TEST_PATTERN
|
||||
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
|
||||
#define LCD_BPP LCD_MONOCHROME
|
||||
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
|
||||
|
||||
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI)
|
||||
#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
|
||||
#include "multa-imx7d_androidthings.h"
|
||||
#endif
|
||||
|
||||
#define PRODUCT_NAME "imx7d"
|
||||
#define VARIANT_NAME "imx7d_multa"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MULTA_IMX7D_ANDROIDTHINGS_H
|
||||
#define __MULTA_IMX7D_ANDROIDTHINGS_H
|
||||
#define TRUSTY_OS_ENTRY 0x9e000000
|
||||
#define TRUSTY_OS_RAM_SIZE 0x2000000
|
||||
#define TEE_HWPARTITION_ID 2
|
||||
#define TRUSTY_OS_MMC_BLKS 0xFFF
|
||||
|
||||
#ifdef CONFIG_IMX_TRUSTY_OS
|
||||
#define NON_SECURE_FASTBOOT
|
||||
#define TRUSTY_KEYSLOT_PACKAGE
|
||||
#endif
|
||||
#include "mx_android_common.h"
|
||||
|
||||
/* For NAND we don't support lock/unlock */
|
||||
#ifndef CONFIG_NAND_BOOT
|
||||
#define CONFIG_FASTBOOT_LOCK
|
||||
#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
|
||||
#define FSL_FASTBOOT_FB_DEV "mmc"
|
||||
#endif
|
||||
|
||||
#define CONFIG_ANDROID_AB_SUPPORT
|
||||
#define FASTBOOT_ENCRYPT_LOCK
|
||||
|
||||
#define CONFIG_FSL_CAAM_KB
|
||||
#define CONFIG_SHA1
|
||||
#define CONFIG_SHA256
|
||||
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_DEV
|
||||
#undef CONFIG_SYS_MMC_ENV_DEV
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_MMC_ENV_PART
|
||||
#undef CONFIG_SYS_MMC_ENV_PART
|
||||
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYSTEM_RAMDISK_SUPPORT
|
||||
|
||||
|
||||
|
||||
#define CONFIG_AVB_SUPPORT
|
||||
#ifdef CONFIG_AVB_SUPPORT
|
||||
#define CONFIG_SUPPORT_EMMC_RPMB
|
||||
#ifdef CONFIG_SYS_MALLOC_LEN
|
||||
#undef CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
#endif
|
||||
/* fuse bank size in word */
|
||||
/* infact 7D have no enough bits
|
||||
* set this size to 0 will disable
|
||||
* program/read FUSE */
|
||||
#define CONFIG_AVB_FUSE_BANK_SIZEW 0
|
||||
#define CONFIG_AVB_FUSE_BANK_START 0
|
||||
#define CONFIG_AVB_FUSE_BANK_END 0
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue