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MA-14519 Phanbell: Explicitly set buck voltages in SPL 

* Bucks 1-4 will be reconfigured via DVS in the kernel.
* Buck 5 is explicitly set to 1.0V
* Regulator lock/unlock is added, this ensures that in warm or cold
reset the values will be set.

Change-Id: I8d8be74bddbbd081030fe1762b9f9c6534c7fb77
This commit is contained in:
Michael Brooks 2018-11-28 16:53:21 -08:00 committed by Ji Luo
parent be25ff5c10
commit 1f27791878
1 changed files with 19 additions and 10 deletions
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29
board/freescale/imx8mq_aiy/spl.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2019 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -167,23 +167,32 @@ int power_init_board(void)
p = pmic_get("BD71837");
pmic_probe(p);
/* unlock the PMIC regs */
/* Unlock reg */
pmic_reg_write(p, BD71837_REGLOCK, 0x1);
/* Set BUCK2 output for ARM to 0.85v */
pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x0f);
/* Set BUCK5 output for DRAM to 1.0V */
/* 0.70,0.80,0.90,1.00, 1.05,1.10,1.20,1.35 */
pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x3);
/* Set BUCK5 output for DRAM to 0.9V */
pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2);
/* Set BUCK3 output for VDD_GPU_0V9 to 0.90V */
/* 0.7-1.3 (10mVstep) */
pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14);
/* Set BUCK6 output for VDD_3V3 to 3.1V */
pmic_reg_write(p, BD71837_BUCK6_VOLT, 0x1);
/* Set BUCK4 output for VDD_VPU_0V9 to 0.90V */
/* 0.7-1.3 (10mVstep) */
pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14);
/* Set BUCK7 output for VDD_1V8 to 1.695V */
pmic_reg_write(p, BD71837_BUCK7_VOLT, 0x1);
/* Set BUCK2 output for VDD_ARM_0V9 to 0.90V */
/* 0.7-1.3 (10mVstep) */
pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0x14);
/* Set BUCK1 output for VDD_SOC_0V9 to 0.90V */
/* 0.7-1.3 (10mVstep) */
pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x14);
/* lock the PMIC regs */
pmic_reg_write(p, BD71837_REGLOCK, 0x11);
return 0;
}
#endif