MA-14129 Update ddr training code for imx8mq_aiy
Update the ddr training code to work with the atf 2.0. Test: Build and boot on imx8mq aiy 3G board. Change-Id: I8546c34cfa4aeeed819f7797f8362676e420b41f Signed-off-by: Ji Luo <ji.luo@nxp.com>
This commit is contained in:
Ji Luo
parent
589b813043
commit
63dbfc00b9
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@ -42,6 +42,7 @@ config TARGET_IMX8MQ_AIY
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bool "imx8mq_aiy"
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select IMX8MQ
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select SUPPORT_SPL
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select IMX8M_LPDDR4
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config TARGET_IMX8MM_DDR4_VAL
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bool "imx8mm DDR4 validation board"
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@ -8,5 +8,5 @@ obj-y += imx8m_aiy.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_3g.o
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endif
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@ -1,34 +0,0 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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enum fw_type {
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FW_1D_IMAGE,
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FW_2D_IMAGE,
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};
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void ddr_init(void);
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void ddr_load_train_code(enum fw_type type);
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void lpddr4_800M_cfg_phy(void);
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static inline void reg32_write(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline uint32_t reg32_read(unsigned long addr)
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{
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return readl(addr);
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}
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static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline void reg32setbit(unsigned long addr, u32 bit)
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{
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setbits_le32(addr, (1 << bit));
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}
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@ -1,474 +0,0 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include "ddr.h"
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#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
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#define ddr_printf(args...) printf(args)
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#else
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#define ddr_printf(args...)
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#endif
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#include "wait_ddrphy_training_complete.c"
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#ifndef SRC_DDRC_RCR_ADDR
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#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
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#endif
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#ifndef DDR_CSD1_BASE_ADDR
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#define DDR_CSD1_BASE_ADDR 0x40000000
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#endif
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#define SILICON_TRAIN
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volatile unsigned int tmp, tmp_t, i;
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void lpddr4_800MHz_cfg_umctl2(void)
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{
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000304, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000030, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000000, 0x83080020);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000064, 0x006180e0);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d0, 0xc003061B);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d4, 0x009D0000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000d8, 0x0000fe05);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000dc, 0x00d4002d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e0, 0x00310008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e4, 0x00040009);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000e8, 0x0046004d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000ec, 0x0005004d);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000000f4, 0x00000979);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000100, 0x1a203522);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000104, 0x00060630);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000108, 0x070e1214);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000010c, 0x00b0c006);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000110, 0x0f04080f);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000114, 0x0d0d0c0c);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000118, 0x01010007);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000011c, 0x0000060a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000120, 0x01010101);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000124, 0x40000008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000128, 0x00050d01);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000012c, 0x01010008);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000130, 0x00020000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000134, 0x18100002);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000138, 0x00000dc2);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x0000013c, 0x80000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000144, 0x00a00050);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000180, 0x53200018);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000184, 0x02800070);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000188, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00002190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00003190, 0x0397820a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000194, 0x00020103);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a0, 0xe0400018);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a4, 0x00df00e4);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001a8, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b0, 0x00000011);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001b4, 0x0000170a);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c0, 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x000001c4, 0x00000000);
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/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP0(0), 0x00000015);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP4(0), 0x00001F1F);
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/* bank interleave */
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP1(0), 0x00080808);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP5(0), 0x07070707);
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dwc_ddrphy_apb_wr(DDRC_ADDRMAP6(0), 0x08080707);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000240, 0x020f0c54);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000244, 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_IPS_BASE_ADDR(0) + 0x00000490, 0x00000001);
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/* performance setting */
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dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
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dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
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dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
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dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
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dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
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dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
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dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
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dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
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dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
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dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
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dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
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dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
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dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
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dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
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dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
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dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
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}
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void lpddr4_100MHz_cfg_umctl2(void)
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{
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reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c);
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reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x00030410);
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reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x0305090c);
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reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x00505006);
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reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x05040305);
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reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504);
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reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x0a060004);
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reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000090e);
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reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x00000032);
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reg32_write(DDRC_FREQ1_DRAMTMG15(0), 0x00000000);
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reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0036001b);
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reg32_write(DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1);
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reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0020d040);
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reg32_write(DDRC_FREQ1_DFITMG0(0), 0x03818200);
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reg32_write(DDRC_FREQ1_ODTCFG(0), 0x0a1a096c);
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reg32_write(DDRC_FREQ1_DFITMG2(0), 0x00000000);
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reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x00038014);
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reg32_write(DDRC_FREQ1_INIT3(0), 0x00840000);
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reg32_write(DDRC_FREQ1_INIT6(0), 0x0000004d);
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reg32_write(DDRC_FREQ1_INIT7(0), 0x0000004d);
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reg32_write(DDRC_FREQ1_INIT4(0), 0x00310000);
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}
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void lpddr4_25MHz_cfg_umctl2(void)
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{
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reg32_write(DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c);
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reg32_write(DDRC_FREQ2_DRAMTMG1(0), 0x00030410);
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reg32_write(DDRC_FREQ2_DRAMTMG2(0), 0x0305090c);
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reg32_write(DDRC_FREQ2_DRAMTMG3(0), 0x00505006);
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reg32_write(DDRC_FREQ2_DRAMTMG4(0), 0x05040305);
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reg32_write(DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504);
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reg32_write(DDRC_FREQ2_DRAMTMG6(0), 0x0a060004);
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reg32_write(DDRC_FREQ2_DRAMTMG7(0), 0x0000090e);
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reg32_write(DDRC_FREQ2_DRAMTMG14(0), 0x00000032);
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reg32_write(DDRC_FREQ2_DRAMTMG15(0), 0x00000000);
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reg32_write(DDRC_FREQ2_DRAMTMG17(0), 0x0036001b);
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reg32_write(DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1);
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reg32_write(DDRC_FREQ2_RFSHCTL0(0), 0x0020d040);
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reg32_write(DDRC_FREQ2_DFITMG0(0), 0x03818200);
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reg32_write(DDRC_FREQ2_ODTCFG(0), 0x0a1a096c);
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reg32_write(DDRC_FREQ2_DFITMG2(0), 0x00000000);
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reg32_write(DDRC_FREQ2_RFSHTMG(0), 0x0003800c);
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reg32_write(DDRC_FREQ2_INIT3(0), 0x00840000);
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reg32_write(DDRC_FREQ2_INIT6(0), 0x0000004d);
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reg32_write(DDRC_FREQ2_INIT7(0), 0x0000004d);
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reg32_write(DDRC_FREQ2_INIT4(0), 0x00310000);
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}
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int get_imx8m_baseboard_id(void);
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void ddr_cfg_phy(void);
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void ddr_init(void)
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{
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int board_id = 0;
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board_id = get_imx8m_baseboard_id();
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if ((board_id == ENTERPRISE_MICRON_1G) ||
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(board_id == ENTERPRISE_HYNIX_1G)) {
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/** Initialize DDR clock and DDRC registers **/
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reg32_write(0x3038a088,0x7070000);
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reg32_write(0x3038a084,0x4030000);
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reg32_write(0x303a00ec,0xffff);
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tmp=reg32_read(0x303a00f8);
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tmp |= 0x20;
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reg32_write(0x303a00f8,tmp);
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reg32_write(0x30391000,0x8f000000);
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reg32_write(0x30391004,0x8f000000);
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reg32_write(0x30360068,0xece580);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x80;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp |= 0x200;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x20;
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reg32_write(0x30360060,tmp);
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tmp=reg32_read(0x30360060);
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tmp &= ~0x10;
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reg32_write(0x30360060,tmp);
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do{
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tmp=reg32_read(0x30360060);
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if(tmp&0x80000000) break;
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}while(1);
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reg32_write(0x30391000,0x8f000006);
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reg32_write(0x3d400304,0x1);
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reg32_write(0x3d400030,0x1);
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reg32_write(0x3d400000,0xa1080020);
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reg32_write(0x3d400028,0x0);
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reg32_write(0x3d400020,0x203);
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reg32_write(0x3d400024,0x186a000);
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reg32_write(0x3d400064,0x610090);
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reg32_write(0x3d4000d0,0xc003061c);
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reg32_write(0x3d4000d4,0x9e0000);
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reg32_write(0x3d4000dc,0xd4002d);
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reg32_write(0x3d4000e0,0x310008);
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reg32_write(0x3d4000e8,0x66004a);
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reg32_write(0x3d4000ec,0x16004a);
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reg32_write(0x3d400100,0x1a201b22);
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reg32_write(0x3d400104,0x60633);
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reg32_write(0x3d40010c,0xc0c000);
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reg32_write(0x3d400110,0xf04080f);
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reg32_write(0x3d400114,0x2040c0c);
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reg32_write(0x3d400118,0x1010007);
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reg32_write(0x3d40011c,0x401);
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reg32_write(0x3d400130,0x20600);
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reg32_write(0x3d400134,0xc100002);
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reg32_write(0x3d400138,0x96);
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reg32_write(0x3d400144,0xa00050);
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reg32_write(0x3d400180,0x3200018);
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reg32_write(0x3d400184,0x28061a8);
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reg32_write(0x3d400188,0x0);
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reg32_write(0x3d400190,0x497820a);
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reg32_write(0x3d400194,0x80303);
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reg32_write(0x3d4001a0,0xe0400018);
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reg32_write(0x3d4001a4,0xdf00e4);
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reg32_write(0x3d4001a8,0x80000000);
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reg32_write(0x3d4001b0,0x11);
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reg32_write(0x3d4001b4,0x170a);
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reg32_write(0x3d4001c0,0x1);
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reg32_write(0x3d4001c4,0x1);
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||||
reg32_write(0x3d4000f4,0x639);
|
||||
reg32_write(0x3d400108,0x70e1214);
|
||||
reg32_write(0x3d400200,0x1f);
|
||||
reg32_write(0x3d40020c,0x0);
|
||||
reg32_write(0x3d400210,0x1f1f);
|
||||
reg32_write(0x3d400204,0x80808);
|
||||
reg32_write(0x3d400214,0x7070707);
|
||||
reg32_write(0x3d400218,0xf070707);
|
||||
reg32_write(0x3d402020,0x1);
|
||||
reg32_write(0x3d402024,0x518b00);
|
||||
reg32_write(0x3d402050,0x20d040);
|
||||
reg32_write(0x3d402064,0x14001f);
|
||||
reg32_write(0x3d4020dc,0x940009);
|
||||
reg32_write(0x3d4020e0,0x310000);
|
||||
reg32_write(0x3d4020e8,0x66004a);
|
||||
reg32_write(0x3d4020ec,0x16004a);
|
||||
reg32_write(0x3d402100,0xb070508);
|
||||
reg32_write(0x3d402104,0x3040b);
|
||||
reg32_write(0x3d402108,0x305090c);
|
||||
reg32_write(0x3d40210c,0x505000);
|
||||
reg32_write(0x3d402110,0x4040204);
|
||||
reg32_write(0x3d402114,0x2030303);
|
||||
reg32_write(0x3d402118,0x1010004);
|
||||
reg32_write(0x3d40211c,0x301);
|
||||
reg32_write(0x3d402130,0x20300);
|
||||
reg32_write(0x3d402134,0xa100002);
|
||||
reg32_write(0x3d402138,0x20);
|
||||
reg32_write(0x3d402144,0x220011);
|
||||
reg32_write(0x3d402180,0xa70006);
|
||||
reg32_write(0x3d402190,0x3858202);
|
||||
reg32_write(0x3d402194,0x80303);
|
||||
reg32_write(0x3d4021b4,0x502);
|
||||
reg32_write(0x3d400244,0x0);
|
||||
reg32_write(0x3d400250,0x29001505);
|
||||
reg32_write(0x3d400254,0x2c);
|
||||
reg32_write(0x3d40025c,0x5900575b);
|
||||
reg32_write(0x3d400264,0x9);
|
||||
reg32_write(0x3d40026c,0x2005574);
|
||||
reg32_write(0x3d400300,0x16);
|
||||
reg32_write(0x3d400304,0x0);
|
||||
reg32_write(0x3d40030c,0x0);
|
||||
reg32_write(0x3d400320,0x1);
|
||||
reg32_write(0x3d40036c,0x11);
|
||||
reg32_write(0x3d400400,0x111);
|
||||
reg32_write(0x3d400404,0x10f3);
|
||||
reg32_write(0x3d400408,0x72ff);
|
||||
reg32_write(0x3d400490,0x1);
|
||||
reg32_write(0x3d400494,0x1110d00);
|
||||
reg32_write(0x3d400498,0x620790);
|
||||
reg32_write(0x3d40049c,0x100001);
|
||||
reg32_write(0x3d4004a0,0x41f);
|
||||
reg32_write(0x30391000,0x8f000004);
|
||||
reg32_write(0x30391000,0x8f000000);
|
||||
reg32_write(0x3d400030,0xa8);
|
||||
do{
|
||||
tmp=reg32_read(0x3d400004);
|
||||
if(tmp&0x223) break;
|
||||
}while(1);
|
||||
reg32_write(0x3d400320,0x0);
|
||||
reg32_write(0x3d000000,0x1);
|
||||
reg32_write(0x3d4001b0,0x10);
|
||||
reg32_write(0x3c040280,0x0);
|
||||
reg32_write(0x3c040284,0x1);
|
||||
reg32_write(0x3c040288,0x2);
|
||||
reg32_write(0x3c04028c,0x3);
|
||||
reg32_write(0x3c040290,0x4);
|
||||
reg32_write(0x3c040294,0x5);
|
||||
reg32_write(0x3c040298,0x6);
|
||||
reg32_write(0x3c04029c,0x7);
|
||||
reg32_write(0x3c044280,0x0);
|
||||
reg32_write(0x3c044284,0x1);
|
||||
reg32_write(0x3c044288,0x2);
|
||||
reg32_write(0x3c04428c,0x3);
|
||||
reg32_write(0x3c044290,0x4);
|
||||
reg32_write(0x3c044294,0x5);
|
||||
reg32_write(0x3c044298,0x6);
|
||||
reg32_write(0x3c04429c,0x7);
|
||||
reg32_write(0x3c048280,0x0);
|
||||
reg32_write(0x3c048284,0x1);
|
||||
reg32_write(0x3c048288,0x2);
|
||||
reg32_write(0x3c04828c,0x3);
|
||||
reg32_write(0x3c048290,0x4);
|
||||
reg32_write(0x3c048294,0x5);
|
||||
reg32_write(0x3c048298,0x6);
|
||||
reg32_write(0x3c04829c,0x7);
|
||||
reg32_write(0x3c04c280,0x0);
|
||||
reg32_write(0x3c04c284,0x1);
|
||||
reg32_write(0x3c04c288,0x2);
|
||||
reg32_write(0x3c04c28c,0x3);
|
||||
reg32_write(0x3c04c290,0x4);
|
||||
reg32_write(0x3c04c294,0x5);
|
||||
reg32_write(0x3c04c298,0x6);
|
||||
reg32_write(0x3c04c29c,0x7);
|
||||
|
||||
/* Configure DDR PHY's registers */
|
||||
ddr_cfg_phy();
|
||||
|
||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
||||
reg32_write(DDRC_SWCTL(0), 0x0000);
|
||||
/*
|
||||
* ------------------- 9 -------------------
|
||||
* Set DFIMISC.dfi_init_start to 1
|
||||
* -----------------------------------------
|
||||
*/
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000030);
|
||||
reg32_write(DDRC_SWCTL(0), 0x0001);
|
||||
|
||||
/* wait DFISTAT.dfi_init_complete to 1 */
|
||||
tmp_t = 0;
|
||||
while(tmp_t==0){
|
||||
tmp = reg32_read(DDRC_DFISTAT(0));
|
||||
tmp_t = tmp & 0x01;
|
||||
tmp = reg32_read(DDRC_MRSTAT(0));
|
||||
}
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0000);
|
||||
|
||||
/* clear DFIMISC.dfi_init_complete_en */
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000010);
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000011);
|
||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
||||
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
/*
|
||||
* set SWCTL.sw_done to enable quasi-dynamic register
|
||||
* programming outside reset.
|
||||
*/
|
||||
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
|
||||
;
|
||||
|
||||
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
|
||||
while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
|
||||
;
|
||||
|
||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
||||
/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
|
||||
/* enable port 0 */
|
||||
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
|
||||
/* enable DDR auto-refresh mode */
|
||||
tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1;
|
||||
reg32_write(DDRC_RFSHCTL3(0), tmp);
|
||||
} else {
|
||||
/* Default use 3G DDR */
|
||||
/* change the clock source of dram_apb_clk_root */
|
||||
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_CLR(1),(0x7<<24)|(0x7<<16));
|
||||
reg32_write(CCM_IP_CLK_ROOT_GEN_TAGET_SET(1),(0x4<<24)|(0x3<<16));
|
||||
|
||||
/* disable the clock gating */
|
||||
reg32_write(0x303A00EC,0x0000ffff);
|
||||
reg32setbit(0x303A00F8,5);
|
||||
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
|
||||
|
||||
dram_pll_init(SSCG_PLL_OUT_800M);
|
||||
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
|
||||
|
||||
/* Configure uMCTL2's registers */
|
||||
lpddr4_800MHz_cfg_umctl2();
|
||||
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
|
||||
reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
|
||||
|
||||
reg32_write(DDRC_DBG1(0), 0x00000000);
|
||||
tmp = reg32_read(DDRC_PWRCTL(0));
|
||||
reg32_write(DDRC_PWRCTL(0), 0x000000a8);
|
||||
/* reg32_write(DDRC_PWRCTL(0), 0x0000018a); */
|
||||
reg32_write(DDRC_SWCTL(0), 0x00000000);
|
||||
reg32_write(DDRC_DDR_SS_GPR0, 0x01);
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000010);
|
||||
|
||||
/* Configure LPDDR4 PHY's registers */
|
||||
lpddr4_800M_cfg_phy();
|
||||
|
||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
||||
reg32_write(DDRC_SWCTL(0), 0x0000);
|
||||
/*
|
||||
* ------------------- 9 -------------------
|
||||
* Set DFIMISC.dfi_init_start to 1
|
||||
* -----------------------------------------
|
||||
*/
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000030);
|
||||
reg32_write(DDRC_SWCTL(0), 0x0001);
|
||||
|
||||
/* wait DFISTAT.dfi_init_complete to 1 */
|
||||
tmp_t = 0;
|
||||
while(tmp_t==0){
|
||||
tmp = reg32_read(DDRC_DFISTAT(0));
|
||||
tmp_t = tmp & 0x01;
|
||||
tmp = reg32_read(DDRC_MRSTAT(0));
|
||||
}
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0000);
|
||||
|
||||
/* clear DFIMISC.dfi_init_complete_en */
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000010);
|
||||
reg32_write(DDRC_DFIMISC(0), 0x00000011);
|
||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
||||
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
/*
|
||||
* set SWCTL.sw_done to enable quasi-dynamic register
|
||||
* programming outside reset.
|
||||
*/
|
||||
reg32_write(DDRC_SWCTL(0), 0x00000001);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
|
||||
;
|
||||
|
||||
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
|
||||
while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
|
||||
;
|
||||
|
||||
reg32_write(DDRC_PWRCTL(0), 0x00000088);
|
||||
/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
|
||||
/* enable port 0 */
|
||||
reg32_write(DDRC_PCTRL_0(0), 0x00000001);
|
||||
tmp = reg32_read(DDRC_CRCPARSTAT(0));
|
||||
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0);
|
||||
lpddr4_100MHz_cfg_umctl2();
|
||||
lpddr4_25MHz_cfg_umctl2();
|
||||
reg32_write(DDRC_SWCTL(0), 0x1);
|
||||
|
||||
/* wait SWSTAT.sw_done_ack to 1 */
|
||||
while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0)
|
||||
;
|
||||
|
||||
reg32_write(DDRC_SWCTL(0), 0x0);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,104 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/sections.h>
|
||||
|
||||
#include "ddr.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define IMEM_LEN 32768//23400 //byte
|
||||
#define DMEM_LEN 16384//1720 //byte
|
||||
#define IMEM_2D_OFFSET 49152
|
||||
|
||||
#define IMEM_OFFSET_ADDR 0x00050000
|
||||
#define DMEM_OFFSET_ADDR 0x00054000
|
||||
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
|
||||
|
||||
/* We need PHY iMEM PHY is 32KB padded */
|
||||
void ddr_load_train_code(enum fw_type type)
|
||||
{
|
||||
u32 tmp32, i;
|
||||
u32 error = 0;
|
||||
unsigned long pr_to32, pr_from32;
|
||||
unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
|
||||
unsigned long imem_start = (unsigned long)&_end + fw_offset;
|
||||
unsigned long dmem_start = imem_start + IMEM_LEN;
|
||||
|
||||
pr_from32 = imem_start;
|
||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
|
||||
for(i = 0x0; i < IMEM_LEN; ){
|
||||
tmp32 = readl(pr_from32);
|
||||
writew(tmp32 & 0x0000ffff, pr_to32);
|
||||
pr_to32 += 4;
|
||||
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
|
||||
pr_to32 += 4;
|
||||
pr_from32 += 4;
|
||||
i += 4;
|
||||
}
|
||||
|
||||
pr_from32 = dmem_start;
|
||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
|
||||
for(i = 0x0; i < DMEM_LEN;){
|
||||
tmp32 = readl(pr_from32);
|
||||
writew(tmp32 & 0x0000ffff, pr_to32);
|
||||
pr_to32 += 4;
|
||||
writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
|
||||
pr_to32 += 4;
|
||||
pr_from32 += 4;
|
||||
i += 4;
|
||||
}
|
||||
|
||||
printf("check ddr4_pmu_train_imem code\n");
|
||||
pr_from32 = imem_start;
|
||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
|
||||
for(i = 0x0; i < IMEM_LEN;){
|
||||
tmp32 = (readw(pr_to32) & 0x0000ffff);
|
||||
pr_to32 += 4;
|
||||
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
|
||||
|
||||
if(tmp32 != readl(pr_from32)){
|
||||
printf("%lx %lx\n", pr_from32, pr_to32);
|
||||
error++;
|
||||
}
|
||||
pr_from32 += 4;
|
||||
pr_to32 += 4;
|
||||
i += 4;
|
||||
}
|
||||
if(error){
|
||||
printf("check ddr4_pmu_train_imem code fail=%d\n",error);
|
||||
}else{
|
||||
printf("check ddr4_pmu_train_imem code pass\n");
|
||||
}
|
||||
|
||||
printf("check ddr4_pmu_train_dmem code\n");
|
||||
pr_from32 = dmem_start;
|
||||
pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
|
||||
for(i = 0x0; i < DMEM_LEN;){
|
||||
tmp32 = (readw(pr_to32) & 0x0000ffff);
|
||||
pr_to32 += 4;
|
||||
tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
|
||||
if(tmp32 != readl(pr_from32)){
|
||||
printf("%lx %lx\n", pr_from32, pr_to32);
|
||||
error++;
|
||||
}
|
||||
pr_from32 += 4;
|
||||
pr_to32 += 4;
|
||||
i += 4;
|
||||
}
|
||||
|
||||
if(error){
|
||||
printf("check ddr4_pmu_train_dmem code fail=%d",error);
|
||||
}else{
|
||||
printf("check ddr4_pmu_train_dmem code pass\n");
|
||||
}
|
||||
}
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __LPDDR4_DVFS_H__
|
||||
#define __LPDDR4_DVFS_H__
|
||||
#include <asm/arch/ddr.h>
|
||||
|
||||
#define DFILP_SPT
|
||||
|
||||
#define ANAMIX_PLL_BASE_ADDR 0x30360000
|
||||
#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
|
||||
#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
|
||||
#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
|
||||
|
||||
#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
|
||||
#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
|
||||
#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
|
||||
#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
|
||||
|
||||
/* 2D share & weight */
|
||||
#define LPDDR4_2D_WEIGHT 0x1f7f
|
||||
#define LPDDR4_2D_SHARE 1
|
||||
#define LPDDR4_CATRAIN_3200_1d 0
|
||||
#define LPDDR4_CATRAIN_400 0
|
||||
#define LPDDR4_CATRAIN_100 0
|
||||
#define LPDDR4_CATRAIN_3200_2d 0
|
||||
|
||||
#define WR_POST_EXT_3200 /* recommened to define */
|
||||
|
||||
/* lpddr4 phy training config */
|
||||
/* for LPDDR4 Rtt */
|
||||
#define LPDDR4_RTT40 6
|
||||
#define LPDDR4_RTT48 5
|
||||
#define LPDDR4_RTT60 4
|
||||
#define LPDDR4_RTT80 3
|
||||
#define LPDDR4_RTT120 2
|
||||
#define LPDDR4_RTT240 1
|
||||
#define LPDDR4_RTT_DIS 0
|
||||
|
||||
/* for LPDDR4 Ron */
|
||||
#define LPDDR4_RON34 7
|
||||
#define LPDDR4_RON40 6
|
||||
#define LPDDR4_RON48 5
|
||||
#define LPDDR4_RON60 4
|
||||
#define LPDDR4_RON80 3
|
||||
|
||||
#define LPDDR4_PHY_ADDR_RON60 0x1
|
||||
#define LPDDR4_PHY_ADDR_RON40 0x3
|
||||
#define LPDDR4_PHY_ADDR_RON30 0x7
|
||||
#define LPDDR4_PHY_ADDR_RON24 0xf
|
||||
#define LPDDR4_PHY_ADDR_RON20 0x1f
|
||||
|
||||
/* for read channel */
|
||||
#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
|
||||
#define LPDDR4_PHY_RTT 30
|
||||
#define LPDDR4_PHY_VREF_VALUE 17
|
||||
|
||||
/* for write channel */
|
||||
#define LPDDR4_PHY_RON 30
|
||||
#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
|
||||
#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
|
||||
#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
|
||||
#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
|
||||
#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
|
||||
#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
|
||||
#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
|
||||
#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
|
||||
#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
|
||||
#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
|
||||
#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
|
||||
|
||||
#define LPDDR4_2D_WEIGHT 0x1f7f
|
||||
#define LPDDR4_2D_SHARE 1
|
||||
|
||||
#endif /*__LPDDR4_DVFS_H__ */
|
||||
|
|
@ -1,96 +0,0 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
static inline void poll_pmu_message_ready(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
do {
|
||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
|
||||
} while (reg & 0x1);
|
||||
}
|
||||
|
||||
static inline void ack_pmu_message_recieve(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
|
||||
|
||||
do {
|
||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
|
||||
} while (!(reg & 0x1));
|
||||
|
||||
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
|
||||
}
|
||||
|
||||
static inline unsigned int get_mail(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
poll_pmu_message_ready();
|
||||
|
||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
|
||||
|
||||
ack_pmu_message_recieve();
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static inline unsigned int get_stream_message(void)
|
||||
{
|
||||
unsigned int reg, reg2;
|
||||
|
||||
poll_pmu_message_ready();
|
||||
|
||||
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
|
||||
|
||||
reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
|
||||
|
||||
reg2 = (reg2 << 16) | reg;
|
||||
|
||||
ack_pmu_message_recieve();
|
||||
|
||||
return reg2;
|
||||
}
|
||||
|
||||
static inline void decode_major_message(unsigned int mail)
|
||||
{
|
||||
ddr_printf("[PMU Major message = 0x%08x]\n", mail);
|
||||
}
|
||||
|
||||
static inline void decode_streaming_message(void)
|
||||
{
|
||||
unsigned int string_index, arg __maybe_unused;
|
||||
int i = 0;
|
||||
|
||||
string_index = get_stream_message();
|
||||
ddr_printf(" PMU String index = 0x%08x\n", string_index);
|
||||
while (i < (string_index & 0xffff)){
|
||||
arg = get_stream_message();
|
||||
ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
|
||||
i++;
|
||||
}
|
||||
|
||||
ddr_printf("\n");
|
||||
}
|
||||
|
||||
void wait_ddrphy_training_complete(void)
|
||||
{
|
||||
unsigned int mail;
|
||||
while (1) {
|
||||
mail = get_mail();
|
||||
decode_major_message(mail);
|
||||
if (mail == 0x08) {
|
||||
decode_streaming_message();
|
||||
} else if (mail == 0x07) {
|
||||
printf("Training PASS\n");
|
||||
break;
|
||||
} else if (mail == 0xff) {
|
||||
printf("Training FAILED\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -20,14 +20,16 @@
|
|||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include "ddr/ddr.h"
|
||||
#include <asm/arch/imx8m_ddr.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern struct dram_timing_info dram_timing_3g;
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
/* ddr init */
|
||||
ddr_init();
|
||||
ddr_init(&dram_timing_3g);
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ CONFIG_SDP_LOADADDR=0x40400000
|
|||
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
|
||||
CONFIG_NOT_UUU_BUILD=y
|
||||
CONFIG_APPEND_BOOTARGS=y
|
||||
|
|
|
|||
|
|
@ -74,3 +74,4 @@ CONFIG_SDP_LOADADDR=0x40400000
|
|||
CONFIG_SPL_USB_HOST_SUPPORT=y
|
||||
CONFIG_SPL_USB_GADGET_SUPPORT=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
|
|
|
|||
Loading…
Reference in New Issue