nrhw20: review, cleanup
This commit is contained in:
Rene Straub
parent
7518ca5631
commit
756fa2b3e3
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@ -39,6 +39,7 @@ int bd_get_context(BD_Context *bdctx, uint32_t i2caddress, uint32_t offset)
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bd_bool_t rc;
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uint8_t bdHeader[8];
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void* pBdData = NULL;
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/* Read header bytes from beginning of EEPROM */
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if (i2c_read( i2caddress, offset, 2, bdHeader, BD_HEADER_LENGTH )) {
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debug("%s() Can't read BD header from EEPROM\n", __func__);
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@ -170,6 +171,7 @@ int bd_get_prodname(char *prodname, size_t len)
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void bd_get_hw_version(int* ver, int* rev)
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{
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// TODO: Warum static?
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static uint8_t hwver;
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static uint8_t hwrev;
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@ -1,8 +1,9 @@
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/*
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* board.c
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*
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* Board functions for TI AM335X based boards
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* Board functions for Netmodule NRHW 20, based on AM335x EVB
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*
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* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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@ -44,14 +45,39 @@
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* NRHW 20 GPIOs
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*
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* GPIO0_2: RST_GNSS~
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* GPIO0_3: GEOFENCE_GNSS
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* GPIO0_4: RTK_STAT_GNSS
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* GPIO0_5: EXTINT_GNSS
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* GPIO0_6: TIMEPULSE_GNSS
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*
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* GPIO0_16: RST_PHY~
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* GPIO0_17: PMIC FAULT
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* GPIO0_27: RST_SHIELD~
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* GPIO0_31: GSM_WAKE
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*
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* GPIO1_14: DIG_OUT
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* GPIO1_15: DIG_IN
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* GPIO1_20: BT_EN
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* GPIO1_21: GSM_PWR_EN
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* GPIO1_25: RST_GSM
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* GPIO1_26: WLAN_EN
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* GPIO1_27: WLAN_IRQ
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*
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* GPIO3_0: BUTTON
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* GPIO3_4: PCIe_IO.WAKE
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* GPIO3_9: PCIe_IO.W_DIS
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* GPIO3_10: PCIe_IO.RST
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* GPIO3_17: SIM_SEL
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* GPIO3_21: RST_HUB~ (USB)
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*/
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
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#define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
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#define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
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#define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
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#define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
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#define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
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#define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
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#define NETBIRD_GPIO_RST_PHY_N GPIO_TO_PIN(0, 16)
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#define NETBIRD_GPIO_PWR_GSM GPIO_TO_PIN(1, 21)
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@ -99,6 +125,7 @@ static int _bd_init(void)
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}
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bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
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return 0;
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}
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@ -117,7 +144,9 @@ struct serial_device *default_serial_console(void)
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return &eserial1_device;
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}
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else {
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return &eserial2_device;
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return &eserial1_device;
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/* TODO: Check */
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/* return &eserial2_device; */
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}
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}
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@ -142,7 +171,7 @@ static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_netbird_emif_reg_data = {
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = 0x61A, /* 32ms > 85°C */
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.sdram_tim1 = 0x0AAAE51B,
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@ -213,7 +242,11 @@ const struct dpll_params *get_dpll_ddr_params(void)
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void set_uart_mux_conf(void)
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{
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#ifdef NRHW20_ON_HW16_MODE
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enable_uart0_disabled_pin_mux();
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#else
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disable_uart0_pin_mux();
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#endif
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enable_uart1_pin_mux();
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}
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@ -237,7 +270,7 @@ void sdram_init(void)
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config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
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&ddr3_netbird_data,
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&ddr3_netbird_cmd_ctrl_data,
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&ddr3_netbird_emif_reg_data, 0);
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&ddr3_emif_reg_data, 0);
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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@ -435,7 +468,7 @@ int board_init(void)
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enable_ext_usb();
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printf("OSC: %lu Hz\n", get_osclk());
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printf("OSC: %lu MHz\n", get_osclk()/1000000);
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return 0;
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}
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@ -549,7 +582,7 @@ static void get_hw_version(void)
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/* add hardware versions to environment */
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bd_get_hw_version(&hw_ver, &hw_rev);
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printf("HW16: V%d.%d\n", hw_ver, hw_rev);
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printf("HW20: V%d.%d\n", hw_ver, hw_rev);
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snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
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snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
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setenv("add_version_bootargs", new_env);
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@ -12,18 +12,27 @@
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#define _BOARD_H_
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/*
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* We have three pin mux functions that must exist. We must be able to enable
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* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
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* uart0, for initial output and i2c2 to read the main EEPROM. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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#ifdef NRHW20_ON_HW16_MODE
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void enable_uart0_disabled_pin_mux(void);
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#else
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void disable_uart0_pin_mux(void);
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#endif
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void enable_uart1_pin_mux(void);
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/*
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void enable_uart2_pin_mux(void);
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void enable_uart3_pin_mux(void);
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void enable_uart4_pin_mux(void);
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void enable_uart5_pin_mux(void);
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*/
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void enable_i2c0_pin_mux(void);
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void enable_i2c2_pin_mux(void);
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void enable_board_pin_mux(void);
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#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
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@ -40,4 +40,3 @@ int read_file(const char* filename, char *buf, int size)
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return len;
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}
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@ -1,7 +1,8 @@
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/*
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* am335x_evm.h
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* am335x_nrhw20.h
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -16,6 +17,16 @@
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#ifndef __CONFIG_AM335X_NRHW20_H
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#define __CONFIG_AM335X_NRHW20_H
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/* TODO:
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* When this define is set, the code is still running on NBHW16
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* It allows to prepare stuff for NRHW20, without loosing test capability
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* on existing HW
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*/
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#define NRHW20_ON_HW16_MODE
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#include <configs/ti_am335x_common.h>
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#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
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@ -101,7 +112,8 @@
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#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
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#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_CONS_INDEX 2 /* Use UART1 as standard UART (1 = UART0) */
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#define CONFIG_CONS_INDEX 1 /* Use UART1 as standard UART (1 = UART0) */
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/* TODO: Check whether CONFIG_CONS_INDEX can be removed --> menuconfig */
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#define CONFIG_CMD_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
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@ -217,6 +229,7 @@
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#endif
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/* Network. */
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/* TODO: Check CONFIG_PHY_GIGE, we don't have GigE */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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@ -241,7 +254,7 @@
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#define CONFIG_CMD_PXE
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/* Never enable ISO it is broaken and can lead to a crash */
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/* Never enable ISO it is broken and can lead to a crash */
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#undef CONFIG_ISO_PARTITION
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#endif /* ! __CONFIG_AM335X_NRHW20_H */
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