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MLK-20902 imx8mm_evk: Change VDD_DRAM to 0.975v 

According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage
of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC
does not support 0.95v output. We change the voltage to 0.975v as
the note in datasheet mentioned it is acceptable and supported.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
This commit is contained in:
Ye Li 2019-02-10 19:17:18 -08:00
parent 2f3e58c8e9
commit a726a0c38b
1 changed files with 2 additions and 2 deletions
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4
board/freescale/imx8mm_evk/spl.c
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@ -180,8 +180,8 @@ int power_init_board(void)
/* increase VDD_SOC to typical value 0.85v before first DRAM access */
pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
/* increase VDD_DRAM to 0.9v for 3Ghz DDR */
pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
#ifndef CONFIG_IMX8M_LPDDR4
/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */