MLK-20886-1 misc: MU: Add MU driver to communicate with M4
Add a common iMX MU driver in misc uclass to communicate with M4. The MU message format is defined to use 4 words as below, the driver will use all 4 TR/RR in MU to pass one message |WORD 0 | WORD 1 | WORD 2 | WORD 3 | |SEQ | TYPE | PAYLOAD ADDRESS | PAYLOAD LENGTH | - SEQ: A sequence id starts from 0 and increases for each request message - TYPE: 0x1: Request. Message sent from AP will set to this value. 0x2: Response. Message responded from M4 set to this value. 0x3: MU A side is ready. 0x4: MU B side is ready. - PAYLOAD ADDRESS: A pointer to the memory address where the uplayer message is stored - PAYLOAD LENGTH: The uplayer message length Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit aba0e51cc397e1d98be950f9c15619de06ebf782)
This commit is contained in:
Ye Li
parent
d903cd890d
commit
b5c9636a96
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@ -119,6 +119,13 @@ config MXC_OCOTP
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Programmable memory pages that are stored on the some
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Freescale i.MX processors.
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config IMX_M4_MU
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bool "Enable i.MX MU Driver to communicate with Cortex M4"
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depends on MISC
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help
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If you say Y here to enable Message Unit driver to work with
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Cortex M4 core on AMP Freescale i.MX processors.
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config NUVOTON_NCT6102D
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bool "Enable Nuvoton NCT6102D Super I/O driver"
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help
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@ -17,6 +17,7 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
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obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
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obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
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obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
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obj-$(CONFIG_IMX_M4_MU) += imx_m4_mu.o
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endif
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obj-$(CONFIG_FSL_IIM) += fsl_iim.o
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obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
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@ -0,0 +1,241 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/root.h>
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#include <dm/device-internal.h>
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#include <asm/mach-imx/sci/sci.h>
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#include <linux/iopoll.h>
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#include <misc.h>
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#include <imx_m4_mu.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mu_type {
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u32 tr[4];
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u32 rr[4];
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u32 sr;
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u32 cr;
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};
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struct imx_m4_mu {
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struct mu_type *base;
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};
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#define MU_CR_GIE_MASK 0xF0000000u
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#define MU_CR_RIE_MASK 0xF000000u
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#define MU_CR_GIR_MASK 0xF0000u
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#define MU_CR_TIE_MASK 0xF00000u
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#define MU_CR_F_MASK 0x7u
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#define MU_SR_TE0_MASK BIT(23)
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#define MU_SR_RF0_MASK BIT(27)
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#define MU_TR_COUNT 4
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#define MU_RR_COUNT 4
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static inline void mu_hal_init(struct mu_type *base)
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{
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/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
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clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
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MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
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}
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static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
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{
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u32 mask = MU_SR_TE0_MASK >> reg_index;
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u32 val;
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int ret;
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assert(reg_index < MU_TR_COUNT);
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debug("sendmsg sr 0x%x\n", readl(&base->sr));
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/* Wait TX register to be empty. */
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ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
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if (ret < 0) {
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debug("%s timeout\n", __func__);
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return -ETIMEDOUT;
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}
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debug("tr[%d] 0x%x\n",reg_index, msg);
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writel(msg, &base->tr[reg_index]);
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return 0;
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}
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static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
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{
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u32 mask = MU_SR_RF0_MASK >> reg_index;
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u32 val;
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int ret;
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assert(reg_index < MU_TR_COUNT);
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debug("receivemsg sr 0x%x\n", readl(&base->sr));
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/* Wait RX register to be full. */
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ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
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if (ret < 0) {
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debug("%s timeout\n", __func__);
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return -ETIMEDOUT;
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}
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*msg = readl(&base->rr[reg_index]);
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debug("rr[%d] 0x%x\n",reg_index, *msg);
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return 0;
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}
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static int mu_hal_poll_receive(struct mu_type *base, ulong rx_timeout)
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{
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u32 mask = MU_SR_RF0_MASK;
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u32 val;
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int ret;
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debug("receivemsg sr 0x%x\n", readl(&base->sr));
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/* Wait RX register to be full. */
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ret = readl_poll_timeout(&base->sr, val, val & mask, rx_timeout);
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if (ret < 0) {
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debug("%s timeout\n", __func__);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int imx_m4_mu_read(struct mu_type *base, void *data)
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{
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union imx_m4_msg *msg = (union imx_m4_msg *)data;
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int ret;
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u8 count = 0;
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if (!msg)
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return -EINVAL;
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/* Read 4 words */
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while (count < 4) {
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ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
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&msg->data[count]);
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if (ret)
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return ret;
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count++;
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}
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return 0;
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}
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static int imx_m4_mu_write(struct mu_type *base, void *data)
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{
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union imx_m4_msg *msg = (union imx_m4_msg *)data;
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int ret;
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u8 count = 0;
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if (!msg)
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return -EINVAL;
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/* Write 4 words */
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while (count < 4) {
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ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
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msg->data[count]);
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if (ret)
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return ret;
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count++;
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}
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return 0;
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}
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/*
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* Note the function prototype use msgid as the 2nd parameter, here
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* we take it as no_resp.
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*/
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static int imx_m4_mu_call(struct udevice *dev, int resp_timeout, void *tx_msg,
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int tx_size, void *rx_msg, int rx_size)
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{
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struct imx_m4_mu *priv = dev_get_priv(dev);
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int ret;
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if (resp_timeout < 0)
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return -EINVAL;
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if (tx_msg) {
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ret = imx_m4_mu_write(priv->base, tx_msg);
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if (ret)
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return ret;
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}
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if (rx_msg) {
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if (resp_timeout) {
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ret = mu_hal_poll_receive(priv->base, resp_timeout);
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if (ret)
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return ret;
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}
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ret = imx_m4_mu_read(priv->base, rx_msg);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int imx_m4_mu_probe(struct udevice *dev)
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{
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struct imx_m4_mu *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = (struct mu_type *)addr;
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debug("mu base 0x%lx\n", (ulong)priv->base);
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/* U-Boot not enable interrupts, so need to enable RX interrupts */
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mu_hal_init(priv->base);
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return 0;
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}
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static int imx_m4_mu_remove(struct udevice *dev)
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{
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return 0;
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}
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static int imx_m4_mu_bind(struct udevice *dev)
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{
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debug("%s(dev=%p)\n", __func__, dev);
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return 0;
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}
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static struct misc_ops imx_m4_mu_ops = {
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.call = imx_m4_mu_call,
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};
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static const struct udevice_id imx_m4_mu_ids[] = {
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{ .compatible = "fsl,imx-m4-mu" },
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{ }
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};
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U_BOOT_DRIVER(imx_m4_mu) = {
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.name = "imx_m4_mu",
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.id = UCLASS_MISC,
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.of_match = imx_m4_mu_ids,
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.probe = imx_m4_mu_probe,
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.bind = imx_m4_mu_bind,
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.remove = imx_m4_mu_remove,
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.ops = &imx_m4_mu_ops,
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.priv_auto_alloc_size = sizeof(struct imx_m4_mu),
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};
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@ -0,0 +1,26 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*
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*/
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#ifndef __IMX_M4_MU_H__
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#define __IMX_M4_MU_H__
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enum imx_m4_msg_type {
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MU_MSG_REQ = 0x1, /* request message sent from A side */
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MU_MSG_RESP = 0x2, /* response message from B side for request */
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MU_MSG_READY_A = 0x3, /* A side notifies ready */
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MU_MSG_READY_B = 0x4, /* B side notifies ready */
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};
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union imx_m4_msg {
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struct {
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u32 seq;
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u32 type;
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u32 buffer;
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u32 size;
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} format;
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u32 data[4];
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};
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#endif
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