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ram: k3-ddrss: Fix a ddr4 controller stall 

The DDR4 controller might stall indefinitely if we access the same
register twice withing a short time interval. This commit makes sure we
reuse the previously read value so that we don't have to access twice.
See this article for more information:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1057242/am6442-access-to-ddr4-controller-register-stalls-indefinitely-while-in-lpddr4-frequency-update
This commit is contained in:
Stefan Eichenberger 2023-02-07 09:20:15 +01:00 committed by Alexandre Bard
parent fd4ed6b7e8
commit dc375987b0
1 changed files with 1 additions and 4 deletions
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5
drivers/ram/k3-ddrss/k3-ddrss.c
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@ -241,15 +241,13 @@ static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
}
}
static u32 dram_class = DENALI_CTL_0_DRAM_CLASS_LPDDR4;
static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
@ -263,7 +261,6 @@ static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{
u32 dram_class;
int ret;
lpddr4_privatedata *pd = &ddrss->pd;