ENGR00315894-77 mx6: soc: Add vadc power up/down function
Add vadc power up/down function. When gis enable in uboot, the CSI0 input mux select setting to vadc module, clean the bit when gis disabled Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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@ -128,6 +128,9 @@ int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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void vadc_power_up(void);
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void vadc_power_down(void);
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void pcie_power_up(void);
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void pcie_power_up(void);
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void pcie_power_off(void);
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void pcie_power_off(void);
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int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
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int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
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@ -392,6 +392,56 @@ static void set_preclk_from_osc(void)
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}
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}
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#ifdef CONFIG_MX6SX
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#ifdef CONFIG_MX6SX
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void vadc_power_up(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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u32 val;
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/* csi0 */
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val = readl(&iomux->gpr[5]);
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val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
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val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
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writel(val, &iomux->gpr[5]);
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/* Power on vadc analog
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* Power down vadc ext power */
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val = readl(GPC_BASE_ADDR + 0);
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val &= ~0x60000;
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writel(val, GPC_BASE_ADDR + 0);
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/* software reset afe */
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val = readl(&iomux->gpr[1]);
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writel(val | 0x80000, &iomux->gpr[1]);
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udelay(10*1000);
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/* Release reset bit */
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writel(val & ~0x80000, &iomux->gpr[1]);
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/* Power on vadc ext power */
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val = readl(GPC_BASE_ADDR + 0);
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val |= 0x40000;
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writel(val, GPC_BASE_ADDR + 0);
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}
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void vadc_power_down(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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u32 val;
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/* Power down vadc ext power
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* Power off vadc analog */
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val = readl(GPC_BASE_ADDR + 0);
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val &= ~0x40000;
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val |= 0x20000;
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writel(val, GPC_BASE_ADDR + 0);
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/* clean csi0 connect to vadc */
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val = readl(&iomux->gpr[5]);
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val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
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writel(val, &iomux->gpr[5]);
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}
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void pcie_power_up(void)
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void pcie_power_up(void)
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{
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{
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set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
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set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */
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