Add the input and output delay values for the available speed modes
for the MMC controller for mmc1/mmc2 for the am62p5 allowing it
to operate at the highest speed modes available, exclude SDR12 since
the speed mode did pass validation.
The higher speed modes have not been finalized yet, but the process
is to set the base value, then update if characterization says
otherwise.
For mmc0, sync with TI's v6.1 kernel.
Signed-off-by: Judith Mendez <jm@ti.com>
After leaving the Partial-IO mode or other deep sleep states, the IO
isolation needs to be removed. This routine is shared by at least am62,
am62a and am62p.
The original function for testing was developed by
Akashdeep Kaur <a-kaur@ti.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Add support for signing, detection and loading of FSSTUB images for
for HSSE and HSFS AM62P devices. Based on the binman code for AM625
with updates to the filenames and load address.
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Vishal Mahaveer <vishalm@ti.com>
Add NAND support for A53 SPL and u-boot.
For A53 SPL & u-boot we use NAND overlay to add NAND support.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
move main_i2c0, main-i2c0-pins-default, and tca9554
definitions to where they belong i.e. k3-am642-evm.dts
k3-am642-r5-evm.dts is not cleaned up like in upstream
to include k3-am642-evm.dts so we have to add the
main-i2c0-pins-default and tca9554 nodes to it
as well.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Add in the input and output delay values for the available speed modes
for the MMC controller for eMMC for the am62p5 allowing it to operate
that the highest speed modes available.
The patch is labeled as a HACK because the HS200 and HS400 values have
not been finalized as of yet even though they have been tested.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
The AM62Px SoC uses a central Device Management and Security Controller
(DMSC) processor that manages all the low-level device controls
including the system-wide SoC reset. The system-wide reset is managed
through the system reset driver.
Add a sysreset controller node as a child of the dmsc node to enable
the "reset" command from U-Boot prompt for the K3 AM62p5 SK EVM.
This is based on commit a97ee92e4a ("arm: dts: k3-am642-evm: Add sysreset controller node")
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Add support for signing, detection and loading of FSSTUB images for
for HSSE, HSFS and GP AM62a devices. Based on the binman code for AM625
with updates to the filenames and load address.
Signed-off-by: Vibhore Vardhan <vibhore@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Tested-by: Vishal Mahaveer <vishalm@ti.com>
ti,syscon-phy-pll-refclk property in the USB expects the wkup_conf to
be syscon compatible to setup the regmap. So update wkup_conf compatible
until the dependency of such nodes on wkup_conf are resolved.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
There are a few updates from TI's Linux mostly centered around
out-of-box remote core demo enablement and we added the bootph-all
property to sdchi0 to enable eMMC as a boot method.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Thanks to the CONFIG_DEFAULT_DEVICE_TREE option in the defconfig the
correct device tree blobs are being built for each uboot stage. However
rather than relying on this add a am62p5 target to the arm/dts/Makefile
Signed-off-by: Bryan Brattlof <bb@ti.com>
Pull in the device tree source files for TI's am62p5 SoCs needed to boot
the board from v6.6-rc5. These are an early release with only the
peripherals to boot the board via UART boot
[bb@ti.com: used DTBs from TI's v6.1 kernel]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Introduce the basic files needed to support the am62px family of SoCs
Co-developed-by: Hari Hagalla <hnagalla@ti.com>
Signed-off-by: Hari Hagalla <hnagalla@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Introduce the basic functions and definitions needed to properly
initialize Ti's am62p family of SoCs
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Currently for the K3 generation of SoCs there are more SoCs that utilize
the split firmware approach than the combined DMSC firmware. Invert the
logic to avoid adding more and more SoCs to this list.
[bb@ti.com: rebased on TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot
[bb@ti.com: rebased to TI's 2023.04 uboot]
Signed-off-by: Bryan Brattlof <bb@ti.com>
BOOT_DEVICE_SPINAND and BOOT_DEVICE_UART have same index of 0x7, this
leads to attempting SPINAND boot during UART boot. Fix this by
allocating unique value to BOOT_DEVICE_SPINAND. While at that move it
out of unused list as SPINAND boot is very much supported on AM62x SoCs.
Fixes: 8c7827f522 ("arm: mack-k3: am62x: Add SPI NAND as a boot device")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
spi-tx-bus-width is set as 8 in SoM dtsi, but set to 1 in R5 common
proc board dts, which seems wrong. SPI NOR requires a 8D reset before
probe starts using 0x66+0x99 op, but that will fail if the flash tx
width is set as 1.
Set spi-tx-bus-width to 8 in R5 common proc board dtsi also.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Currently J721E defines only the main_esm in DTS. Add node for mcu_esm
as well.
According to J721E TRM (12.11.2.2 ESM Environment) [1], we see that the
interrupt line from ESMi (main_esm) is routed to MCU_ESM (mcu_esm). This
is MCU_ESM0_LVL_IN_95 with interrupt ID 95. Configure mcu_esm
accordingly so that errors from main_esm are routed to mcu_esm and
handled.
[1] https://www.ti.com/lit/zip/spruil1
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Set boot core-opts to enable split mode for MCU R5 cluster by default.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Previously, MCU R5F runs DM on core0, and core1 sits waiting in WFI mode.
The support to shut the core1 and use it for loading other firmware,
while DM runs on core0, has been added. Enable split-mode on the MCU R5F.
Use the newly introduced compatible for MCU R5F cores.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The following commits adds the configuration of firewalls required to
protect ATF and OP-TEE memory region from non-secure reads and
writes using master and slave firewalls present in our K3 SOCs.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
For readability during configuring firewalls, adding k3-security.h file
and including it in k3-binman.dtsi to be accessible across K3 SoCs
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Patch adds the ESM instances for j721s2. It has 3 instances.
One in the main domain and two in the mcu-wakeup domian.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Patch adds the ESM instances for j784s4. It has 3 instances.
One in the main domain and two in the mcu-wakeup domian.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Samuel Dolt
Stefan Eichenberger
Judith Mendez
Udit Kumar
Markus Schneider-Pargmann
Dhruva Gole
Roger Quadros
Vignesh Raghavendra
Mattijs Korpershoek
Vibhore Vardhan
Ravi Gunasekaran
Bryan Brattlof
Nishanth Menon
Apurva Nandan
Neha Malcom Francis
Manorit Chawdhry
Keerthy