The HABv4 implementation in ROM checks if HAB major version
in IVT header is 4.x.
The current implementation in hab.c code is only validating
HAB v4.0 and HAB v4.1 and may be incompatible with newer
HABv4 versions.
Modify verify_ivt_header() function to align with HABv4
implementation in ROM code.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 33f51b401dffa393274a28f9d49a87af3eb02fe0)
When booting in low power or dual boot modes the M4 binary is
authenticated by the M4 ROM code.
Add an option in hab_status command so users can retrieve M4 HAB
failure and warning events.
=> hab_status m4
Secure boot disabled
HAB Configuration: 0xf0, HAB State: 0x66
No HAB Events Found!
Add command documentation in mx6_mx7_secure_boot.txt guide.
As HAB M4 API cannot be called from A7 core the code is parsing
the M4 HAB persistent memory region. The HAB persistent memory
stores HAB events, public keys and others HAB related information.
The HAB persistent memory region addresses and sizes can be found
in AN12263 "HABv4 RVT Guidelines and Recommendations".
Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
(cherry picked from commit 0efff16579fabcf57acb9c8857afac8fb58de355)
Update SCFW API to v1.3 at below commit. A new API sc_pm_set_boot_parm
is added.
commit c5ef21f894de0ac8329f0fe540331a272fcd1461
Author: Chuck Cannon <chuck.cannon@nxp.com>
Date: Tue Feb 26 15:36:53 2019 -0600
SCF-352: Add more to SECO test.
Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit e79209e4174054bb328bae441bf8ab3c1312ee4e)
When M4 is booted by ROM, we have to enable RPMSG in kernel, so need
to select the -rpmsg.dtb. If M4 is not enabled, use default kernel dtb.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 8a57be45e18295ce1b19799723775cf5b205281d)
The iMX8MQLite new part will not disable DCSS in fuse. So change
the codes to check the DCSS fuse before disable relevant FDT nodes
and u-boot HDMI splash screen.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 9e6ab0397b8d94de8b904250884726e58633066b)
Update to latest SCFW API with below commit. Add version API and
remove some resource ids.
commit 004247e14afc74a21d65569415c4b2e35bfaabc3
Author: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Date: Thu Feb 14 14:55:12 2019 -0800
SCF-341 Fix bug in setting large slice clock divider
Incorrect mask was applied when clearing out the bits in the
DSC large slice divider.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 745f2e597613e96f1ac630e842faafdc060ee029)
We use a glue layer to link the low level MU driver and virtual drivers.
This glue layer is named to virtual service (iMX VService). Virtual service
provides unified interfaces for setup connection with M4, get message buffer
and send/receive message, etc.
Multiple virtual drivers (i2c, gpio, etc)
|
iMX Vservice
|
imx_mu_m4 driver
For each virtual device, by default, the Vservice uses the device node property
"fsl,vservice-mu" to specify the MU node handler. A override function is also provided,
so te ARCH level can define its rule. We will use the override function for dynamically
select MU on 8QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4d872794cae55ffb654a55646bbf231e8d864e13)
Sync the SCFW API to latest commit below:
commit 0721a2af721fca45e9d7e9b673b669ffab9aca7f
Author: Glen Wienecke <glen.wienecke@nxp.com>
Date: Sun Feb 10 19:16:56 2019 -0600
SCF-296: Partition reboot should not reset FSPI/OCRAM if in use
- Update ss_rsrc_reset to return BUSY error if FSPI/OCRAM in use
- Update pm_update_ridx to skip power transition if FSPI/OCRAM in use
- For user_mode update requests, reflect mode achieved after pm_update_ridx
- Add PM SVC call to get active mode (user_mode not accurate during transitions)
- Undo some MISRA updates that changed ss_rsrc_reset to void function
Signed-off-by: Glen Wienecke <glen.wienecke@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Update SCFW API to below commit which has deprecated APIs with
misc_seco prefix.
commit 30b8f67097d65c6e22f218b106aeafdc636aece3
Author: Chuck Cannon <chuck.cannon@nxp.com>
Date: Fri Jan 25 15:24:55 2019 -0600
SCF-60: MISRA fixes.
Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
The CAAM driver in u-boot will use JR0 by default, but for
imx8q, both JR0 and JR1 are assigned to SECO and A core
should never access them.
Power on the JR3 in this patchset and use it to complete
the CAAM operations for imx8q.
Test: CAAM self test cases pass for imx8q.
Change-Id: Ie3d77d1f2910e7f4c257c797c12b5c8a30ad936a
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Add new u-boot command "imx_tamper" to configure and check the tamper pins.
The codes are used for reference and test. So command is disabled at default,
user can enable it by adding CONFIG_IMX_TAMPER=y to defconfig
The iMX7D has 10 tamper pins those can be used for SNVS tamper detection.
Tamper 9 pin is NVCC_DRAM power switch for LPSR by default.
It must be fused to tamper function by command
=> fuse prog -y 1 3 0x80000000
Otherwise, SNVS power consumption would be high
When tamper is detected, CPU can't enter/stay in SNVS mode,
the tamper must be cleared and disabled before enter SNVS.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Shaojun Wang <shaojun.wang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Add the NAND support to SPL container parser and enable it for imx8qxp arm2
nand reworked board.
The SPL NAND will read from nandfit mtdpart (128MB offset) to parsing the entire
boot image and get the 3rd container from it. This requires burning tool (uuu)
to program the entire boot image into nandfit.
Signed-off-by: Ye Li <ye.li@nxp.com>
Update SCFW API from below SCFW commit which provides
the API to get seco events
commit 50355d4b11b089be8fc1bc13afa7da001b081a44
Author: Chuck Cannon <chuck.cannon@nxp.com>
Date: Mon Jan 14 12:30:42 2019 -0600
SCF-275: Fix monitor error on command 'event'.
Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
The previous LPCG register addresses seem wrong. By checking the LPCG with
JTAG, the ipg_clk, ipg_s_clk, and perclk uses one register as the standard
implementation method, not use 3 registers.
Signed-off-by: Ye Li <ye.li@nxp.com>
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.
Signed-off-by: Ye Li <ye.li@nxp.com>
Each module may have one or more lpcg registers for SW/HW enabling its
clocks. Add lpcg register address and its driver for accessing lpcg.
Signed-off-by: Ye Li <ye.li@nxp.com>
The get_boot_device will return USB type from ROM info if booting from
serial download, so change the is_boot_from_usb to use this function.
Signed-off-by: Ye Li <ye.li@nxp.com>
Because the ROM info on iMX7D does not set device type to USB when booting
from serial download mode, we have to use the mechanism on mx6 to implement
the is_boot_from_usb. The original implementation is checking USB controller
register, it can't work correctly after any USB functionality is run in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Rename the gd flag GD_FLG_ARCH_MX6_USB_BOOT to GD_FLG_ARCH_IMX_USB_BOOT,
and move it to mach-imx/sys_proto.h since we will also use it on mx7.
Signed-off-by: Ye Li <ye.li@nxp.com>
u-boot currently needs information from ATF to know if
OP-TEE os has been loaded.
this information is transmitted via bootargs.
this patch enables saving those bootargs into a structure.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Introduce xen header files from Linux Kernel commit
e2b623fbe6a3("Merge tag 's390-4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Generate the key blob and store it to the last block of boot1 partition
after setting the rpmb key. The key blob should be checked in spl and be
passed to Trusty OS if it's valid. If the key blob are damaged, RPMB
storage proxy service will return fail and should make the device hang.
Test: Build and boot ok on imx8qm/qxp.
Change-Id: Ia274cd72109ab6ae15920e91b2a2008e1f1e667c
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
i.MX7ULP B0 silicon has below updates in iomux
- GPIO function input buffer enable (IBE)/output buffer enable (OBE) is
now controlled by RGPIO module. IOMUXC IBE/OBE is used as an override.
- LPUART2_TX (I/O) to PTB12 (ALT4)
- LPUART2_RX (I) to PTB13 (ALT4)
- USB0_ID (I) to PTC13 (ALT11), PTC18 (ALT11) and PTC19 (ALT10)
- VIU_DE (I) to PTC18 (ALT12), PTC19 (ALT12) and PTE5 (ALT12)
- RTC_CLKOUT (O) to PTB5 (ALT11) and PTB14 (ALT11)
- SEC_VIO_B (I) to PTB4 (ALT11)
- Added new Input Selection Registers
PSMI1_USB0_ID Address: 0x40ac_0338 To select USB_ID input pad/source
PSMI1_VIU_DE Address: 0x40ac_033c To select VIU_DE input pad/source
Copy the imx7ulp-pinfunc.h from latest kernel dts
(commit 18cdeadfe1967ea33d3bdfc7ccead6d6d06a98a6), and update
the mx7ulp-pins.h accordingly.
Signed-off-by: Ye Li <ye.li@nxp.com>
Update API files generated from latest SCFW commit:
commit b5dbcf59157cf758da2b96c395e3f4cb2674437f
Author: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Date: Sat Oct 27 02:04:47 2018 -0500
SCF-248 Fix Linux boot fail on iMX8QX
Signed-off-by: Ye Li <ye.li@nxp.com>
iMX8MM family has several variant parts below.
Add CPU type and relevant updates
i.MX 8M Mini Quad Full featured, 4x A53
i.MX 8M Mini QuadLite No VPU, 4x A53
i.MX 8M Mini Dual Full featured, 2x A53
i.MX 8M Mini DualLite No VPU, 2x A53
i.MX 8M Mini Solo Full featured, 1x A53
i.MX 8M Mini SoloLite No VPU, 1x A53
Signed-off-by: Ye Li <ye.li@nxp.com>
Since commit 8891410c72 ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:
Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [<412c00dc>] lr : [<8ff560bc>]
reloc pc : [<c8b6d0dc>] lr : [<178030bc>]
sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8
r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000
r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000
r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063
Flags: nzCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.
Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Currently the is_boot_from_usb is checking the USB PHY Powerdown bit. This
way has a defect that if we run any usb function in u-boot the checking will
always return true.
This patch improves the way to avoid such problem above. A new arch-specific flag is
added to indicate if it is USB boot. We check the USB PHY PWD bit at early of boot
stage then set that flag. So any following calling of is_boot_from_usb will return
correct value.
Signed-off-by: Ye Li <ye.li@nxp.com>
This is a hack for imx8qm-mek, since the offset of the flash.bin image
on eMMC differs when compared to imx8qxp-mek. Basically, the default value
is 32K, but for 8qm-mek it's 0. This can go away once the qm and qxp get
aligned (again) from this point of view.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
For LPDDR4 and DDR4, we use the same dram_timing struct
to config parameters. rename the 'lpddr4_timing' to
'dram_timing' for common use.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
For LPDDR4 or DDR4, the ddr phy train flow is the same.
So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'.
make it more common for reuse and move it to driver/ddr/imx8m/.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
When running uuu on iMX8MQ, meet USB enumeration failure in fastboot.
The root cause is a cache issue in dwc3 driver. When the issue happens, the ctrl_req in
gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev)
is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB
controller, any accessing to usb_composite_dev variable will cause the cache refill, then
when setup transfer is completed, reading the setup data in ctrl_req will gets old value from
cache not from memory.
The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory.
so it still needs cache maintain operations before/after HW accessing. Since the cache flush or
invalidate bases on cache line, so when the allocated memory size is not cache line aligned,
potentially it may meet such issue.
This patch modifies the dma_alloc_coherent API to round the size to cache line aligned.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This transforms almost all related functions from mmc specific to device
independent. This allows the container size to be computed from QSPI and other
future devices that will be supported for boot.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Add i.MX6ULZ support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
CPU 2/3 are fused on iMX8MD, power down the two cores in SPL to
save power.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
iMX8MQ has two variant versions: iMX8MD and iMX8MQLite. Add dummy CPU ID
for these two, and check the fuses to get correct versions.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add common CHIP_REV_2_1 for chip revision 2.1
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f7fc83ffb0f204d9f6ec6c77c08d23869d9ecde4)
Add "clocks" command to list clocks values for core and some peripherals
on QM/QXP.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c2c9b6487440946a52564ee20c2b1943a4085152)
The QOS relevant registers are not defined in register header file.
When building plugin, these addresses are set to 0 and cause plugin
failed.
Move the QOS registers definitions from set_epdc_qos to register
header file to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
As u-boot use no SMP so not care shareable cache.
But the Trusty OS will check the memory attr for
inner shareable.
So add the flag to mark the memory to be inner
shareable for ARMv7 only.
Change-Id: I322101d01346834aa3fad30ac788fe394336aa1a
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
Enable TZASC on i.MX 8mm.
There is a need on 8MM to enable
the BYPASS ID SWAP bit (GPR10 bit 1) in order
for GPU not to generated AXI bus errors.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add relevant functions and files to parse the container image set from mmc/sd
and get the total size of it. So we can get the offset of u-boot-atf.bin image
when it is padded to container image set at 1KB alignment position.
Signed-off-by: Ye Li <ye.li@nxp.com>
the dram init is board related. But there is still some common
part can be reused on different board. The basic flow is common
for all the board. only the DDRC and DDR PHY config register setting
is different on different board. So extract the LPDDR4 init common
flow to make it more generic. baord level only need to provide
the DDRC and PHY config register parameter to the common code to finish
the dram init.
the same method can be use for DDR4. will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
Enable the video PLL (594Mhz) and clocks in displaymix. Add the LCDIF clock
set interface to change its dot clock rate.
Update registers header file for LCDIF base address.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 3c27bc4bfa35dbebee2b5797c9137a2257946eca)
Breno Lima
Leonard Crestez
Ye Li
Ji Luo
Silvano di Ninno
Peng Fan
Bai Ping
Teo Hall
Abel Vesa
Haibo Chen
Haoran.Wang