Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
The mscale B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
It returns a magic number 0xff0055aa.
Update get_cpu_rev to support this way, also enable OCOTP clock to allow
access OCOTP register.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 866631c2140b9352c6f74ec36d1a51fea40c0445)
The PLL used on i.MX8MM is different from i.MX8MQ,
so add new clock_imx8mm.c dedicated for i.MX8MM,
Currently use two new files for i.MX8MM, in future
the code could be restructed to share to avoid
code duplication.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 4415e28950b1baf62a9b9e3c819d93e7deba0cad)
Bai Ping
Ye Li
Peng Fan