nmhw24: fix LED assignment

- upper/lower LED was swapped

arch/arm/Kconfig

@@ -406,6 +406,14 @@ config TARGET_AM335X_NMHW21
         select DM_SERIAL
         select DM_GPIO
 
+config TARGET_AM335X_NMHW24
+        bool "Support am335x_nmhw24"
+        select CPU_V7
+        select SUPPORT_SPL
+        select DM
+        select DM_SERIAL
+        select DM_GPIO
+
 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
 	select CPU_V7
@@ -906,6 +914,7 @@ source "board/nm/netbird/Kconfig"
 source "board/nm/netbird_v2/Kconfig"
 source "board/nm/nrhw20/Kconfig"
 source "board/nm/nmhw21/Kconfig"
+source "board/nm/nmhw24/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"

board/nm/nmhw24/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NMHW24
+
+config SYS_BOARD
+        default "nmhw24"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_nmhw24"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+	default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/nmhw24/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o fileaccess.o da9063.o

board/nm/nmhw24/board.h

@@ -0,0 +1,28 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void disable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
+#endif

board/nm/nmhw24/da9063.c

@@ -0,0 +1,139 @@
+/*
+ * da9063.c
+ *
+ * Dialog DA9063 PMIC
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+
+#include "da9063.h"
+
+
+static int da9063_i2c_bus = 0;
+static int bus_claimed = 0;
+
+
+static int switch_i2c_bus(void)
+{
+	int old_bus;
+
+	old_bus = i2c_get_bus_num();
+	if (old_bus != da9063_i2c_bus) {
+		i2c_set_bus_num(da9063_i2c_bus);
+	}
+
+	bus_claimed++;
+
+	return old_bus;
+}
+
+static void revert_i2c_bus(int bus)
+{
+	if (da9063_i2c_bus != bus) {
+		i2c_set_bus_num(bus);
+	}
+
+	bus_claimed--;
+}
+
+
+void da9063_init(int i2c_bus)
+{
+	da9063_i2c_bus = i2c_bus;
+}
+
+int da9063_claim_i2c_bus(void)
+{
+	return switch_i2c_bus();
+}
+
+void da9063_release_i2c_bus(int bus)
+{
+	revert_i2c_bus(bus);
+}
+
+int da9063_get_reg(uint32_t reg, u8* val)
+{
+	int ret;
+	u8 temp;
+
+	/* Argument check */
+	if ((reg >= 0x200) || (val==0)) {
+		return -1;
+	}
+
+	/* State check. Has bus been claimed */
+	if (bus_claimed == 0) {
+		return -2;
+	}
+
+	*val = 0;
+	if (reg < 0x100) {
+		ret = i2c_read(CONFIG_PMIC_I2C_ADDR+0, reg & 0xFF, 1, &temp, 1);
+	} else {
+		ret = i2c_read(CONFIG_PMIC_I2C_ADDR+1, reg & 0xFF, 1, &temp, 1);
+	}
+
+	if (ret == 0)
+		*val = temp;
+
+	return ret;
+}
+
+int da9063_set_reg(uint32_t reg, u8 val)
+{
+	int ret;
+
+	/* Argument check */
+	if (reg >= 0x200) {
+		return -1;
+	}
+
+	/* State check. Has bus been claimed */
+	if (bus_claimed == 0) {
+		return -2;
+	}
+
+	if (reg < 0x100) {
+		ret = i2c_write(CONFIG_PMIC_I2C_ADDR+0, reg & 0xFF, 1, &val, 1);
+	} else {
+		ret = i2c_write(CONFIG_PMIC_I2C_ADDR+1, reg & 0xFF, 1, &val, 1);
+	}
+
+	if (ret != 0)
+		puts("da9063 write error\n");
+
+	return ret;
+}
+
+void da9063_set_gpio(unsigned bit, int state)
+{
+	int pmic_reg;
+	int ret;
+	u8 bitmask;
+	u8 reg = 0x00;
+
+	if (bit <= 7) {
+		pmic_reg = PMIC_REG_GPIO_MODE0_7;
+		bitmask = 1U << (bit-0);
+	}
+	else  {
+		pmic_reg = PMIC_REG_GPIO_MODE8_15;
+		bitmask = 1U << (bit-8);
+	}
+
+	ret = da9063_get_reg(pmic_reg, &reg);
+
+	if (ret == 0)  {
+		if (state)	reg |=  bitmask;
+		else		reg &= ~bitmask;
+
+		(void)da9063_set_reg(pmic_reg, reg);
+	}
+}

board/nm/nmhw24/da9063.h

@@ -0,0 +1,68 @@
+/*
+ * da9063.c
+ *
+ * Dialog DA9063 PMIC
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef DA9063_H
+#define DA9063_H
+
+// TODO: Add include for uint32_t (stdtypes.h)
+
+
+#define CONFIG_PMIC_I2C_BUS	0
+#define CONFIG_PMIC_I2C_ADDR	0x58	/* Pages 0 and 1, Pages 2 and 3 -> 0x59 */
+
+#define PMIC_REG_STATUS_A	0x01	/* Status of ON_KEY, WAKE, COMP1V2, DVC */
+#define PMIC_REG_CONTROL_D      0x11    /* Control register for blink/watchdog */
+#define PMIC_REG_GPIO14_15      0x1C    /* Configuration of GPIO14/15 (mode, wake) */
+#define PMIC_REG_GPIO_MODE0_7	0x1D	/* Control register for GPIOs 0..7 */
+#define PMIC_REG_GPIO_MODE8_15	0x1E	/* Control register for GPIOs 8..15 */
+
+#define PMIC_REG_BCORE1_CONT	0x21	/* Control register of BCORE1 */
+#define PMIC_REG_BCORE2_CONT	0x20	/* Control register of BCORE2 */
+#define PMIC_REG_BPERI_CONT	0x25	/* Control register of BPERI */
+#define PMIC_REG_BIO_CONT	0x24	/* Control register of BIO */
+#define PMIC_REG_BMEM_CONT	0x23	/* Control register of BMEM */
+
+#define PMIC_REG_LDO3_CONT	0x28	/* Control register of LDO3 */
+#define PMIC_REG_LDO6_CONT	0x2B	/* Control register of LDO6 */
+#define PMIC_REG_LDO7_CONT	0x2C	/* Control register of LDO7 */
+#define PMIC_REG_LDO11_CONT	0x30	/* Control register of LDO11 */
+
+#define PMIC_LDOx_EN_MASK	0x01
+#define PMIC_LDOx_CONF_MASK	0x80
+
+#define PMIC_REG_ID_4_3		0x84
+
+#define PMIC_REG_BUCK_ILIM_A	0x9A
+#define PMIC_REG_BUCK_ILIM_B	0x9B
+#define PMIC_REG_BUCK_ILIM_C	0x9C
+
+#define PMIC_REG_BBAT_CONT	0xC5	/* Control register for backup battery */
+
+#define PMIC_REG_CONFIG_E	0x10A
+#define PMIC_REG_CONFIG_G	0x10C
+#define PMIC_REG_CONFIG_L	0x111
+
+#define PMIC_REG_TRIM_CLDR	0x120	/* Calendar Trim register, 2's complement, 1.9ppm per bit */
+
+#define PMIC_REG_CONFIG_ID	0x184	/* OTP Config ID <ver.rev> */
+
+
+extern void da9063_init(int i2c_bus);
+
+extern int da9063_claim_i2c_bus(void);
+extern void da9063_release_i2c_bus(int bus);
+
+extern int da9063_get_reg(uint32_t reg, u8* val);
+extern int da9063_set_reg(uint32_t reg, u8 val);
+
+extern void da9063_set_gpio(unsigned bit, int state);
+
+
+#endif /* DA9063_H */

board/nm/nmhw24/fileaccess.c

@@ -0,0 +1,42 @@
+#include <common.h>
+#include <fs.h>
+
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	/* File does not exist, do not print an error message */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}

board/nm/nmhw24/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/nmhw24/mux.c

@@ -0,0 +1,231 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* CPU GPIOs
+	*
+	* (A17) GPIO0_2: RST_GNSS~
+	* (A16) GPIO0_5: EXTINT_GNSS
+	* (C18) GPIO0_7: PWM / SHIELD LATCH
+	* (J18) GPIO0_16: RST_PHY~
+	* (U12) GPIO0_27: RST_SHIELD~
+	*
+	* (R14) GPIO1_20: BT_EN
+	* (V15) GPIO1_21: GSM_PWR_EN
+	* (U16) GPIO1_25: RST_GSM
+	* (T16) GPIO1_26: WLAN_EN
+	* (V17) GPIO1_27: WLAN_IRQ
+	*
+	* (C12) GPIO3_17: SIM_SEL
+	*/
+
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},				/* (A17) gpio0[2] */  /* RST_GNSS */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},			/* (A16) gpio0[5] */  /* EXTINT_GNSS */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (C18) gpio0[7] */  /* IO_SHIELD */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},				/* (U12) gpio0[27] */  /* RST_SHIELD~ */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},				/* (R14) gpio1[20] */  /* BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},				/* (V15) gpio1[21] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},				/* (U16) gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},				/* (T16) gpio1[26] */  /* WLAN_EN */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V17) gpio1[27] */  /* WLAN_IRQ */
+
+	/* TODO: What about all the unused GPMC pins ? */
+
+	/* Bank 2 */
+#if 0
+	/* TODO: What is this meant for? */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (R4) gpio2[9] */  /* SYSBOOT_3 */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (T1) gpio2[10] */  /* SYSBOOT_4 */
+
+	/* TODO: Check other unued pins from sysboot block */
+	/* Ensure PU/PD does not work against external signal */
+	/*
+	 * SYSBOOT 0,1,5,12,13 = Low
+	 * SYSBOOT 2 = High
+	 */
+#endif
+
+	/* Bank 3 */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (C12) gpio3[17] */  /* SIM_SEL */
+	{-1}
+};
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1}
+};
+
+/* I2C2 System */
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D17) I2C2_SCL */
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D18) I2C2_SDA */
+	{-1},
+};
+
+/* RMII1: Ethernet Switch */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for PHY) */
+	{-1}
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1}
+};
+
+/* UART0: RS232/RS485 shield mode */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* UART0: Shield I/F (UART, CAN) */
+/* Leave UART0 unconfigured because we want to configure it as needed by Linux (can/spi/uart/etc) */
+/* Mode 7 = GPIO */
+static struct module_pin_mux uart0_disabled_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E15) GPIO1_10 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) GPIO1_11 */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E18) GPIO1_8 */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E17) GPIO1_9 */
+	{-1},
+};
+
+/* UART1: User (Debug/Console) */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D15) uart1_txd */
+	{-1},
+};
+
+/* UART3: GNSS */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (L17) UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (L16) UART3_TXD */
+	{-1}
+};
+
+/* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1}
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1}
+};
+
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c2_pin_mux);
+
+	configure_module_pin_mux(uart3_pin_mux);
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void disable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}

board/nm/nmhw24/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/nmhw24/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

configs/am335x_nmhw24_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NMHW24=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+# CONFIG_BOOTP_PXE_CLIENTARCH is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_FPGA is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_PMIC is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set

include/configs/am335x_nmhw24.h

@@ -0,0 +1,302 @@
+/*
+ * am335x_nmhw24.h
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_NMHW24_H
+#define __CONFIG_AM335X_NMHW24_H
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_OMPAP_WATCHDOG
+#undef CONFIG_SPL_WATCHDOG_SUPPORT
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				0 /* 0 means detect from sysboot1 config */
+#define V_SCLK				(V_OSCK)
+
+#include <config_distro_bootcmd.h>
+
+/* Dynamic override for PHY_ANEG_TIMEOUT value */
+#ifndef CONFIG_SPL_BUILD
+# ifndef __ASSEMBLER__
+int eth_phy_timeout(void);
+# endif
+#endif
+#define PHY_ANEG_TIMEOUT		eth_phy_timeout()
+#define PHY_ANEG_DEFAULT_TIMEOUT	5000
+
+#define CONFIG_ARP_TIMEOUT		200
+#undef CONFIG_NET_RETRY_COUNT
+#define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_BOOTP_MAY_FAIL
+
+#ifndef CONFIG_SPL_BUILD
+
+
+/*
+ * Memory map for booting Linux
+ *
+ * 0x80000000   63MB	KERNEL_ADDR (kernel_addr), kernel execution address
+ * 0x83F00000    1MB	FDT_ADDR (fdt_addr_r), device tree loading address if not included in kernel
+ * 0x84000000  126MB	RD_ADDR (ramdisk_addr_r), ramdisc loading address
+ * 0x8BE00000    2MB	PXE_ADDR (pxefile_addr_r), pxe configuration file (pxe get command)
+ * 0x8C000000    1MB	LOAD_ADDR (load_addr), loading address for generic files
+ * 0x8C100000   63MB	KERNEL_ADDR_R (kernel_addr_r), kernel loading address (will be relocated to kernel_addr)
+ * 0x90000000  256MB	<>, Free space 512MB systems
+ * 0xA0000000  512MB	<>, Free space, 1GB systems only
+ * 0xC0000000		End of RAM
+ */
+
+#define KERNEL_ADDR	"0x80000000"
+#define FDT_ADDR	"0x83F00000"
+#define RD_ADDR		"0x84000000"
+#define PXE_ADDR	"0x8BE00000"
+#define LOAD_ADDR	"0x8C000000"
+#define KERNEL_ADDR_R	"0x8C100000"
+
+#if 0 /* HW20 differences */
+#define LOAD_ADDR			"0x83000000" 8c0000
+#define FDT_ADDR			"0x82000000" 83f000
+#define PXE_ADDR			"0x82800000" 8be000
+#define FDT_HIGH_ADDR			"0x87000000"
+#define INIT_RD_ADDR			"0x88000000"
+#endif
+
+
+/*
+ * Avoid copying ramdisc and dtb above 512MB, as it breaks Linux boot.
+ * -1 means "do not copy" to high address, use in place.
+ */
+#define INITRD_HIGH_ADDR "0x84000000"
+#define FDT_HIGH_ADDR    "0xffffffff"
+
+/* TODO: Check big differences to NMHW20 */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_image=am335x-nmhw24-prod1.dtb\0" \
+	"fdt_addr_r=" FDT_ADDR "\0" \
+	"fdt_high=" FDT_HIGH_ADDR "\0" \
+	"initrd_high=" INITRD_HIGH_ADDR "\0" \
+	"kernel_addr=" KERNEL_ADDR "\0" \
+	"kernel_addr_r=" KERNEL_ADDR_R  "\0" \
+	"load_addr=" LOAD_ADDR "\0" \
+	"pxefile_addr_r=" PXE_ADDR "\0" \
+	"ramdisk_addr_r=" RD_ADDR "\0" \
+	"defaultconsole=ttyS1\0" \
+	"fdt_skip_update=yes\0" \
+	"ethprime=cpsw\0" \
+	"ethopts=ti_cpsw.rx_packet_max=1526\0" \
+	"bootcmd_otenv=ext4load mmc 1:1 $load_addr /boot/loader/uEnv.txt; " \
+			"env import -t $load_addr $filesize; " \
+			"setenv bootargs $bootargs root=/dev/ram0 console=$defaultconsole,115200 " \
+			"$ethopts rw ostree_root=/dev/mmcblk1p1\0" \
+	"bootcmd_rd_in_mmc=ext4load mmc 1:1 $kernel_addr_r /boot$kernel_image; " \
+			"bootm $kernel_addr_r\0" \
+	"bootcmd=run bootcmd_otenv; run bootcmd_rd_in_mmc\0" \
+	"bootdelay=0\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"tftptimeout=2000\0" \
+	"tftptimeoutcountmax=5\0" \
+	"bootpretryperiod=10000\0" \
+	"autoload=false\0" \
+	"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr_r recovery-dtb; " \
+			"setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 " \
+			"debug ethopts; " \
+			"bootz $kernel_addr - $fdt_addr_r\0" \
+	"pxe_recovery=mdio up $ethprime && dhcp && pxe get && pxe boot\0" \
+	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" \
+			/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs internally */
+
+
+#if 0
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_image=kernel.bin\0"	\
+	"fdt_image=openwrt-nrhw20-nb1601.dtb\0"\
+	"modeboot=sdboot\0" \
+	"fdt_addr=" FDT_ADDR "\0" \
+	"kernel_addr=" KERNEL_ADDR "\0" \
+	"load_addr=" LOAD_ADDR "\0" \
+	"root_part=1\0" /* Default root partition, overwritten in board file */ \
+	"defaultconsole=ttyS1\0" /* Default output console */ \
+	"add_sd_bootargs=setenv bootargs $bootargs root=/dev/mmcblk1p$root_part rootfstype=ext4 " \
+			"console=$defaultconsole,115200 rootwait loglevel=4 ti_cpsw.rx_packet_max=1526\0" \
+	"add_version_bootargs=setenv bootargs $bootargs\0" \
+	"fdt_skip_update=yes\0" \
+	"ethprime=cpsw\0" \
+	"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
+	"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
+	"sdboot=if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
+			"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
+			"else run sdbringup; fi; " \
+			"run add_sd_bootargs; run add_version_bootargs; run shieldcmd; " \
+			"bootz $kernel_addr - $fdt_addr; fi\0" \
+	"bootcmd_otenv=ext4load mmc 1:1 $load_addr /boot/loader/uEnv.txt; " \
+			"env import -t $load_addr $filesize; " \
+			"setenv bootargs $bootargs root=/dev/ram0 console=$defaultconsole,115200 " \
+			"$ethopts rw ostree_root=/dev/mmcblk1p1\0" \
+	"bootcmd_rd_in_mmc=ext4load mmc 1:1 $kernel_addr_r /boot$kernel_image; " \
+			"bootm $kernel_addr_r\0" \
+	"bootcmd=run bootcmd_otenv; run bootcmd_rd_in_mmc\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"pxefile_addr_r=" PXE_ADDR "\0" \
+	"fdt_addr_r=" FDT_ADDR "\0" \
+	"fdt_high=" FDT_HIGH_ADDR "\0" \
+	"kernel_addr_r=" KERNEL_ADDR "\0" \
+	"ramdisk_addr_r=" LOAD_ADDR "\0" \
+	"initrd_high=" INIT_RD_ADDR "\0" \
+	"bootpretryperiod=1000\0" \
+	"tftptimeout=2000\0" \
+	"tftptimeoutcountmax=5\0" \
+	"bootpretryperiod=2000\0" \
+	"autoload=false\0" \
+	"shieldcmd=\0" \
+	"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; " \
+			"setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 " \
+			"debug ti_cpsw.rx_packet_max=1526; run shieldcmd; " \
+			"bootz $kernel_addr - $fdt_addr\0" \
+	"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
+	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" \
+			/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
+
+#endif
+
+#endif
+
+/* TODO: Check if ok? */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550_COM1			0x44e09000	/* UART0: XModem Boot */
+#define CONFIG_SYS_NS16550_COM2			0x48022000	/* UART1: eMMC Boot, User UART */
+
+#define CONFIG_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_I2C_SPEED                    100000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   50	/* TODO: Can this be reduced to 20ms */
+
+/* Put Environment in eMMC */
+#define CONFIG_ENV_OFFSET			(512 * 128)	/* @ 512*256 SPL starts */
+#define CONFIG_ENV_SIZE				(4 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV			1
+
+#undef CONFIG_SPL_ENV_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_ONENAND_SUPPORT
+
+/* We need to disable SPI to not confuse the eeprom env driver */
+#undef CONFIG_SPI
+#undef CONFIG_SPI_BOOT
+#undef CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE		MUSB_HOST
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+
+#ifdef CONFIG_USB_MUSB_HOST
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_USB_MUSB_GADGET
+/* Removing USB gadget and can be enabled adter adding support usb DM */
+#ifndef CONFIG_DM_ETH
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+#endif /* CONFIG_DM_ETH */
+#endif /* CONFIG_USB_MUSB_GADGET */
+
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+#endif
+
+/* Network. */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START    0x84000000
+#define CONFIG_SYS_MEMTEST_END      0x87900000
+
+#define CONFIG_CMD_PXE
+
+#define CONFIG_OF_BOARD_SETUP
+
+#define CONFIG_JTAG_MARKER_SPL		0x402FFF00
+#define CONFIG_JTAG_MARKER_UBOOT	0x807FFF00
+
+/* SPL command is not needed */
+#undef CONFIG_CMD_SPL
+
+/* Never enable ISO it is broken and can lead to a crash */
+#undef CONFIG_ISO_PARTITION
+
+#endif	/* ! __CONFIG_AM335X_NMHW24_H */