FIX: [uboot] DUAL CAN termination GPIO numbers

BugzId: 54033

arch/arm/Kconfig

@@ -374,6 +374,22 @@ config TARGET_AM335X_EVM
 	select DM_GPIO
 	select TI_I2C_BOARD_DETECT
 
+config TARGET_AM335X_NETBIRD
+	bool "Support am335x_netbird"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_NETBIRD_V2
+	bool "Support am335x_netbird_v2"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
 	select CPU_V7
@@ -870,6 +886,8 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/imx31_phycore/Kconfig"
 source "board/isee/igep0033/Kconfig"
 source "board/mpl/vcma9/Kconfig"
+source "board/nm/netbird/Kconfig"
+source "board/nm/netbird_v2/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"

arch/arm/cpu/armv7/am33xx/clock_am33xx.c

@@ -21,6 +21,8 @@ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
+struct ctrl_stat *const ctrlstat = (struct ctrl_stat*)CTRL_BASE;
+
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x88,
 	.cm_idlest_dpll		= CM_WKUP + 0x20,
@@ -53,13 +55,13 @@ const struct dpll_regs dpll_ddr_regs = {
 
 struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core_opp100 = {
-		1000, OSC-1, -1, -1, 10, 8, 4};
-const struct dpll_params dpll_mpu = {
-		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-		50, OSC-1, -1, -1, 1, 1, 1};
-const struct dpll_params dpll_per = {
+struct dpll_params dpll_core_opp100 = {
+  1000, OSC-1, -1, -1, 10, 8, 4};
+struct dpll_params dpll_mpu = {
+  MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+struct dpll_params dpll_core = {
+  50, OSC-1, -1, -1, 1, 1, 1};
+struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
 const struct dpll_params *get_dpll_mpu_params(void)
@@ -113,8 +115,25 @@ void setup_clocks_for_console(void)
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
+static inline unsigned long get_osclk_dpll(void)
+{
+	return (get_osclk() / 1000000) - 1;
+}
+
+static inline void am33xx_init_osc_clock(void)
+{
+	unsigned long n = get_osclk_dpll();
+	dpll_mpu_opp100.n = n;
+	dpll_core_opp100.n = n;
+	dpll_mpu.n = n;
+	dpll_core.n = n;
+	dpll_per.n = n;
+}
+
 void enable_basic_clocks(void)
 {
+	am33xx_init_osc_clock();
+
 	u32 *const clk_domains[] = {
 		&cmper->l3clkstctrl,
 		&cmper->l4fwclkstctrl,
@@ -159,3 +178,18 @@ void enable_basic_clocks(void)
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
 }
+
+static unsigned long ram_timings[] = {
+	19200000, 24000000, 25000000, 26000000
+};
+
+unsigned long get_osclk(void)
+{
+	if (V_OSCK != 0) {
+		return V_OSCK;
+	}
+	else {
+		unsigned int sysboot1 = (readl(&ctrlstat->statusreg) >> 22) & 3;
+		return ram_timings[sysboot1];
+	}
+}

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -123,6 +123,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 {
 	int sil_rev;
 
+/* @@nm@@mr@@ Ignore what the fuse says. 
+	We do not want to go higher than 600 MHZ for now. 
+	This should actually not be needed as it should be overwritten
+	in am33xx_spl_board_init anyway. Just to be sure. 
+	-> Remove it, if really not necessary.
+*/
+return MPUPLL_M_600;
+
 	sil_rev = readl(&cdev->deviceid) >> 28;
 
 	if (sil_rev == 1)

arch/arm/cpu/armv7/omap-common/abb.c

@@ -48,7 +48,7 @@ static void abb_setup_timings(u32 setup)
 	 */
 
 	/* calculate SR2_WTCNT_VALUE */
-	sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+	sys_rate = DIV_ROUND_CLOSEST(get_osclk(), 1000000);
 	clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
 	sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
 

arch/arm/cpu/armv7/omap-common/timer.c

@@ -33,6 +33,16 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 #define TIMER_OVERFLOW_VAL	0xffffffff
 #define TIMER_LOAD_VAL		0
 
+static inline unsigned long get_timer_clock(void)
+{
+	if (V_SCLK != 0) {
+		return TIMER_CLOCK;
+	}
+	else {
+		return get_osclk() / (2 << CONFIG_SYS_PTV);
+	}
+}
+
 int timer_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
@@ -55,7 +65,7 @@ ulong get_timer(ulong base)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	long tmo = usec * (get_timer_clock() / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 
 	while (tmo > 0) {
@@ -71,13 +81,13 @@ void __udelay(unsigned long usec)
 ulong get_timer_masked(void)
 {
 	/* current tick value */
-	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	ulong now = readl(&timer_base->tcrr) / (get_timer_clock() / CONFIG_SYS_HZ);
 
 	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
 		gd->arch.tbl += (now - gd->arch.lastinc);
 	} else {	/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (get_timer_clock() /
 				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
 	}
 	gd->arch.lastinc = now;

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h

@@ -32,7 +32,8 @@
 #define CM_DLL_READYST		0x4
 
 extern void enable_dmm_clocks(void);
-extern const struct dpll_params dpll_core_opp100;
+extern unsigned long get_osclk(void);
+extern struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */

arch/arm/include/asm/arch-am33xx/cpu.h

@@ -530,10 +530,12 @@ struct ctrl_dev {
 	unsigned int macid1h;		/* offset 0x3c */
 	unsigned int resv4[4];
 	unsigned int miisel;		/* offset 0x50 */
-	unsigned int resv5[7];
+	unsigned int resv5[4];
+	unsigned int pwmssctrl;		/* offset 0x64 */
+	unsigned int resv6[2];
 	unsigned int mreqprio_0;	/* offset 0x70 */
 	unsigned int mreqprio_1;	/* offset 0x74 */
-	unsigned int resv6[97];
+	unsigned int resv7[97];
 	unsigned int efuse_sma;		/* offset 0x1FC */
 };
 

board/nm/common/bdparser.h

@@ -0,0 +1,569 @@
+#ifndef _BDPARSER_H
+#define _BDPARSER_H
+/******************************************************************************
+ * (c) COPYRIGHT 2009-2011 by NetModule AG, Switzerland.  All rights reserved.
+ *
+ * The program(s) may only be used and/or copied with the written permission
+ * from NetModule AG or in accordance with the terms and conditions stipulated
+ * in the agreement contract under which the program(s) have been supplied.
+ *
+ * PACKAGE : Board descriptor
+ *
+ * ABSTRACT:
+ *  This package implements board descriptor manipulation functions.
+ *
+ * HISTORY:
+ *  Date      Author       Description
+ *  20091106  rb           RFE-FB18392: created
+ *  20100119  rs           Minor cleanup, tags defined
+ *  20100301  rs           Tags redefined
+ *  20100302  sma          RFE-FB18392: created (partition)
+ *  20100322  th           Adaptation WinCE and Win32 (assert)
+ *                         Added get bd info (type and name for standard entries)
+ *                         Adjusted bd tags
+ *                         Added scan entries (init and get next)
+ *                         Added partition info (flags and types)
+ *                         Added uint64 and partition64
+ *                         Changed boolean value true (BD_TRUE to 1)
+ *  20110104  rs           General code cleanup (style guide), added new tags/types
+ *                         Added bufLen parameter for BD_GetInfo()
+ *                         Fixed wrong sizeof type in GetPartition()
+ *                         Changed 64 bit type to "long long" from struct
+ *                         Added BD_VerifySha1Hmac() function
+ *****************************************************************************/
+
+/**
+ * @file
+ * Board descriptor parser.
+ *  Get() functions are implemented for all supported basis data types:
+ *  - 8/16/32 bits unsigned integers
+ *  - void
+ *  - string
+ *  - IPv4 addresses
+ *  - Ethernet MAC addresses
+ */
+
+/**
+
+\mainpage
+
+\section description    Description
+
+This is the generated documentation for the <b>Board Descriptor utilities</b>.
+
+For more details see the Board Descriptor Design Description.
+
+**/
+
+/*--- component configuration ------------------------------------------------*/
+
+/** Select a target or operating system (just one of course) **/
+#undef BD_TARGET_WIN32
+#undef BD_TARGET_WINCE
+#define BD_TARGET_UBOOT
+#undef BD_TARGET_LINUX
+#undef BD_TARGET_VXWORKS
+
+#undef BD_CONF_UNIT_TESTS      /**< define this to include unit test functions */
+
+#undef BD_CONF_WANT_ASSERT     /**< define this to use assert functions */
+
+#undef BD_CONF_HAS_HASH        /**< set to include hash check functions in parser */
+
+
+/** Define external hmac-sha1 function to use */
+#ifdef BD_CONF_HAS_HASH
+  extern int hmac_sha1(const void* key, unsigned int keylen, const void* data, unsigned int dataLen, void* hash);
+
+  #define BD_SHA1_HASH_FUNC(key, keylen, data, dataLen, hash) \
+            hmac_sha1 (key, keylen, data, dataLen, hash)
+#endif
+
+/** Define desired assert function */
+#ifdef BD_CONF_WANT_ASSERT
+  #ifdef BD_TARGET_WINCE
+    #define BD_ASSERT(test)  ASSERT(test)
+  #elif defined(BD_TARGET_WIN32) && !defined(_DEBUG)
+    /* Win32 Release build */
+    #include <stdio.h>
+    #include <stdlib.h>
+    #define BD_ASSERT(test)  { if(!(test)) { printf("BD_ASSERT(%s)\n- file <%s>\n- line <%d>\n", #test, __FILE__, __LINE__ ); exit(1); } }
+  #elif defined(BD_TARGET_LINUX)
+    #include <linux/kernel.h>
+    #define BD_ASSERT(test)  { if(!(test)) { printk(KERN_NOTICE "BD_ASSERT(%s) %s:%d\n", #test, __FILE__, __LINE__ ); } }
+  #else
+    #include <assert.h>
+    #define BD_ASSERT(test)  assert(test)
+  #endif
+#else
+  /* No assertions wanted */
+  #define BD_ASSERT(test)  ((void) 0)
+#endif /* BD_CONF_WANT_ASSERT */
+
+
+
+/*--- defines ----------------------------------------------------------------*/
+
+#define BD_MAX_LENGTH           (4096)    /**< Maximum length of a board descriptor's payload */
+#define BD_MAX_ENTRY_LEN        (512)     /**< Maximum length of a tag value */
+#define BD_HEADER_LENGTH        (8)       /**< Header is 8 bytes long */
+#define BD_MAX_PARTITION_NAME   (16)      /**< Name of partition is at most 16 chars long*/
+
+
+/*--- types ------------------------------------------------------------------*/
+
+/**
+ * Board Descriptor Tags
+ */
+typedef enum _BD_Tags
+{
+  BD_End                =     0,   /**<  "Void"       -> End tag */
+  BD_Serial             =     1,   /**<  "String"     -> Serial number of the equipment */
+  BD_Production_Date    =     2,   /**<  "Date"       -> Production date of the board */
+  BD_Hw_Ver             =     3,   /**<  "UInt8"      -> Hardware version of the equipment (Major HW changes, potentionally SW relevant) */
+  BD_Hw_Rel             =     4,   /**<  "UInt8"      -> Hardware release of the equipment (Minor HW changes, not SW relevant) */
+  BD_Prod_Name          =     5,   /**<  "String"     -> Human readable product name  */
+  BD_Prod_Variant       =     6,   /**<  "UInt16"     -> Product variant */
+  BD_Prod_Compatibility =     7,   /**<  "String"     -> Product compatibility name */
+
+  BD_Eth_Mac            =     8,   /**<  "MAC"        -> MAC address of the ethernet interface */
+  BD_Ip_Addr            =     9,   /**<  "IPV4"       -> IP V4 address (0.0.0.0 = DHCP) */
+  BD_Ip_Netmask         =    10,   /**<  "IPV4"       -> IP V4 address mask */
+  BD_Ip_Gateway         =    11,   /**<  "IPV4"       -> IP V4 address of the default gateway */
+
+  BD_Usb_Device_Id      =    12,   /**<  "UInt16"      -> USB device ID */
+  BD_Usb_Vendor_Id      =    13,   /**<  "UInt16"      -> USB vendor ID */
+
+  BD_Ram_Size           =    14,   /**<  "UInt32"     -> Available RAM size in bytes */
+  BD_Ram_Size64         =    15,   /**<  "UInt64"     -> Available RAM size in bytes */
+  BD_Flash_Size         =    16,   /**<  "UInt32"     -> Available flash size in bytes */
+  BD_Flash_Size64       =    17,   /**<  "UInt64"     -> Available flash size in bytes */
+  BD_Eeeprom_Size       =    18,   /**<  "UInt32"     -> Available EEPROM size in bytes */
+  BD_Nv_Rram_Size       =    19,   /**<  "UInt32"     -> Available EEPROM size in bytes */
+
+  BD_Cpu_Base_Clk       =    20,   /**<  "UInt32"     -> Base clock of the CPU in Hz = external clock input */
+  BD_Cpu_Core_Clk       =    21,   /**<  "UInt32"     -> Core clock of the CPU in Hz */
+  BD_Cpu_Bus_Clk        =    22,   /**<  "UInt32"     -> Bus clock of the CPU in Hz */
+  BD_Ram_Clk            =    23,   /**<  "UInt32"     -> RAM clock in Hz */
+
+  BD_Partition          =    24,   /**<  "Partition"   -> Offset of 1st Uboot partition in the 1st flash device in bytes */
+  BD_Partition64        =    25,   /**<  "Partition64" -> Offset of 1st Uboot partition in the 1st flash device in bytes */
+
+  BD_Lcd_Type           =    26,   /**<  "UInt16"     -> LCD type -> 0 = not present (interpretation can be project specific) */
+  BD_Lcd_Backlight      =    27,   /**<  "UInt8"      -> LCD backlight setting (0 = off; 100=max) */
+  BD_Lcd_Contrast       =    28,   /**<  "UInt8"      -> LCD contrast setting (0 = min; 100=max) */
+  BD_Touch_Type         =    29,   /**<  "UInt16"     -> Touch Screen type --> 0 = not present/defined */
+
+  BD_Manufacturer_Id    =    30,   /**<  "String"     -> Manufacturer id of the produced equipment (i.e. barcode) */
+  BD_Hmac_Sha1_4        =    31,   /**<  "Hash"       -> SHA1 HMAC with 4 byte result */
+  BD_Fpga_Info          =    32,   /**<  "UInt32"     -> FPGA type/location (0xTTPPRRRR TT=FPGA type, PP=Population location, RRRR=Reserved allways 0000) */
+
+  BD_Ui_Adapter_Type    =  4096,   /**<  "UInt16"     -> IV OG2 UI adapterboard type (0 = not present) */
+
+  BD_Pd_Module0         =  4100,
+  BD_Pd_Module1         =  4101,
+  BD_Pd_Module2         =  4102,
+  BD_Pd_Module3         =  4103,
+  BD_Pd_Module4         =  4104,
+  BD_Pd_Module5         =  4105,
+  BD_Pd_Sim             =  4122,
+  PD_Dev_Tree           =  4125,   /**<  "String"     -> Devicetree file name */
+  PD_SerDes             =  4128,   /**<  "Uint16"     -> SERDES Configuration (e.g. NB1800) */
+  PD_Shield             =  4129,   /**<  "String"     -> Shield Population (e.g. CAN/RS485) for NB800 */
+
+  /* project specific tags */
+  BD_BootPart			= 32768,   /**<  "UInt8" */
+
+  BD_None_Type          = 65535,   /**<  "Void"       -> None */
+}
+BD_Tags;
+
+/**
+ * Board Descriptor Tag Types
+ */
+typedef enum _BD_Type
+{
+  BD_Type_End         = 0x00000000,
+  BD_Type_Void        = 0x00000001,
+  BD_Type_UInt8       = 0x00000002,
+  BD_Type_UInt16      = 0x00000003,
+  BD_Type_UInt32      = 0x00000004,
+  BD_Type_UInt64      = 0x00000005,
+  BD_Type_String      = 0x00000010,
+  BD_Type_Date        = 0x00000020,
+  BD_Type_MAC         = 0x00000030,
+  BD_Type_IPV4        = 0x00000040,
+  BD_Type_Partition   = 0x00000050,
+  BD_Type_Partition64 = 0x00000051,
+  BD_Type_HMAC        = 0x00000060,
+  BD_Type_None        = 0xFFFFFFFF,
+}
+BD_Type;
+
+
+typedef unsigned int    bd_uint_t;      /**< Generic UInt */
+typedef unsigned int    bd_size_t;      /**< Size type */
+
+typedef unsigned char   bd_uint8_t;     /**< 8 Bit unsigned integer */
+typedef unsigned short  bd_uint16_t;    /**< 16 Bit unsigned integer */
+typedef unsigned int    bd_uint32_t;    /**< 32 Bit unsigned integer */
+
+#if defined(BD_TARGET_WIN32) || defined (BD_TARGET_WINCE)
+  typedef unsigned __int64 bd_uint64_t;   /**< 64 Bit unsigned integer */
+#else
+  typedef unsigned long long bd_uint64_t; /**< 64 Bit unsigned integer */
+#endif
+
+typedef int             bd_bool_t;      /**< Boolean */
+#define BD_FALSE        0               /**< Boolean FALSE */
+#define BD_TRUE         1               /**< Boolean  TRUE */
+
+typedef struct _BD_Info
+{
+  BD_Tags           tag;
+  BD_Type           type;
+  const char*       pName;
+}
+BD_Info;
+
+typedef struct _BD_Entry
+{
+  bd_uint16_t       tag;           /**< Tag of entry */
+  bd_size_t         len;           /**< Length of entry */
+  bd_uint_t         entry;         /**< Number of entry */
+  const bd_uint8_t* pData;         /**< Pointer to descriptor data of entry */
+}
+BD_Entry;
+
+
+/**
+ * Board Descriptor Context
+ *
+ * This structure is passed to all calls of a Board Descriptor function.
+ * It stores the required context information.
+ * The entries are solely used by the Board Descriptor functions.
+ * They must not be accessed by the user.
+ */
+typedef struct _BD_Context
+{
+  bd_bool_t          headerOk;      /**< True if header check passed else false */
+  bd_bool_t          initialized;   /**< True if data imported (and checked) */
+
+  bd_uint_t          size;          /**< Size of descriptor data */
+  bd_uint_t          entries;       /**< Number of entries found */
+
+  bd_uint16_t        checksum;      /**< Payload checksum contained in the header */
+  const bd_uint8_t*  pData;         /**< Pointer to descriptor data (not header) */
+  const bd_uint8_t*  pDataEnd;      /**< Pointer to end of data */
+}
+BD_Context;
+
+
+/*
+ * Partition Flags
+ */
+typedef enum _BD_Partition_Flags
+{
+  BD_Partition_Flags_None           = 0x00,     /**< No special flags */
+  BD_Partition_Flags_Active         = 0x80,     /**< Partition is active */
+}
+BD_Partition_Flags;
+
+/*
+ * Partition Type
+ */
+typedef enum _BD_Partition_Type
+{
+  BD_Partition_Type_Raw             = 0,        /**< Unspecified type */
+  BD_Partition_Type_Raw_BootLoader  = 1,        /**< Linear bootloader image */
+  BD_Partition_Type_Raw_BBT         = 2,        /**< Bad Block Table */
+  BD_Partition_Type_FS_YAFFS2       = 3,        /**< YAFFS2 Partition */
+  BD_Partition_Type_FS_JFFS2        = 4,        /**< JFFS2 Partition */
+  BD_Partition_Type_FS_FAT16        = 5,        /**< FAT16 Partition */
+  BD_Partition_Type_FS_FAT32        = 6,        /**< FAT32 Partition */
+  BD_Partition_Type_FS_EXFAT        = 7,        /**< EXFAT Partition */
+
+  BD_Partition_Type_Max             = 8,        /**< For error checks */
+}
+BD_Partition_Type;
+
+/*
+ * Partition Options (Partition64 element only)
+ */
+typedef enum _BD_Partition_Options
+{
+  BD_Partition_Opts_None            = 0x00,     /***< No special options */
+  BD_Partition_Opts_ReadOnly        = 0x01,     /***< Partition should be mounted read only */
+  BD_Partition_Opts_OS              = 0x02,     /***< Partition contains operating system (OS) */
+}
+BD_Partition_Options;
+
+/**
+ * Board descriptor type to describe filesystem partitions
+ *
+ * The function BD_GetPartition will directly fill such a structure.
+ */
+typedef struct _BD_PartitionEntry
+{
+  BD_Partition_Flags    flags;
+  BD_Partition_Type     type;
+  bd_uint32_t           offset;
+  bd_uint32_t           size;
+  char                  name[BD_MAX_PARTITION_NAME+1];
+}
+BD_PartitionEntry;
+
+/**
+ * Board descriptor type to describe filesystem partitions
+ *
+ * Extended version with 64 bit addresses and options field.
+ * The function BD_GetPartition64 will directly fill such a structure.
+ */
+typedef struct _BD_PartitionEntry64
+{
+  BD_Partition_Flags    flags;
+  BD_Partition_Type     type;
+  BD_Partition_Options  options;
+  bd_uint64_t           offset;
+  bd_uint64_t           size;
+  char                  name[BD_MAX_PARTITION_NAME+1];
+}
+BD_PartitionEntry64;
+
+
+/*--- function prototypes ----------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Checks a BD header's validity and updates the BD context.
+ *
+ * @param[in,out] pCtx      The context of the BD being checked.
+ * @param[in]     pHeader   Pointer to the BD header
+ * @return        True if the header is valid and the context was updated.
+ *                False if the header s not valid.
+ */
+bd_bool_t BD_CheckHeader( BD_Context* pCtx, const void* pHeader );
+
+/**
+ * Imports BD data from a buffer into a BD context.
+ *
+ * @param[in,out] pCtx      The context into which data is imported.
+ * @param[in]     pData     Pointer to the buffer containing the BD entries.
+ * @return        True if BD entries could be succesfuly imported.
+ *                False if there is an error in the buffer data structure.
+ */
+bd_bool_t BD_ImportData( BD_Context* pCtx, const void* pData );
+
+/**
+ * Checks the existence of a tag in the BD
+ *
+ * @param[in,out] pCtx      The context in which the tag is searched.
+ * @param[in]     tag       Tag being checked.
+ * @param[in]     index     Index of the tag (0=first index).
+ * @return        True if the entry exists in the BD else False.
+ */
+bd_bool_t BD_ExistsEntry( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index );
+
+/**
+ * Get type and name of a tag in the BD info table
+ *
+ * @param[in]     tag       Tag reference.
+ * @param[out]    pType     Type of the tag (0 if not used).
+ * @param[out]    pName     Name of the tag (0 if not used).
+ * @param[in]     bufLen    Length of the pName buffer.
+ *                          If required the returned string for pName will be truncated.
+ * @return        True if the tag in the BD info table exists else False.
+ */
+bd_bool_t BD_GetInfo( bd_uint16_t tag, BD_Type* pType, char* pName, bd_size_t bufLen );
+
+/**
+ * Initialize the entry before use BD_GetNextEntry
+ *
+ * @param[out]    pEntry    BD entry to be initalized.
+ * @return        True if the entry was initialized, fasle otherwise.
+ */
+bd_bool_t BD_InitEntry( BD_Entry* pEntry);
+
+/**
+ * Get type and name of a tag in the BD info table
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[out]    pEntry    BD entry (use BD_InitEntry, not 0 for first ).
+ * @return        True if the tag in the BD info table exists else False.
+ */
+bd_bool_t BD_GetNextEntry( const BD_Context* pCtx, BD_Entry* pEntry );
+
+
+/**
+ * Gets a void value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   True if the value could be found else False.
+ * @return        False if something went wrong dring the parsing else True.
+ */
+bd_bool_t BD_GetVoid( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_bool_t* pResult );
+
+/**
+ * Gets an 8 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt8( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint8_t* pResult );
+
+/**
+ * Gets a 16 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt16( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint16_t* pResult );
+
+/**
+ * Gets a 32 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt32( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult );
+
+/**
+ * Gets a 64 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt64( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint64_t* pResult );
+
+/**
+ * Gets a string value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @param[in]     bufLen    Length of the pResult buffer.
+ * @return        True if the value in pResult is valid else False.
+ *
+ * @note @li The returned string in pResult is null-terminated.
+ *       @li If the buffer is too.small to hold the value the returned string is truncated.
+ */
+bd_bool_t BD_GetString( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, char* pResult, bd_size_t bufLen );
+
+/**
+ * Gets a binary large object (blob) value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @param[in]     bufLen    Length of the pResult buffer.
+ * @param[out]    pReadLen  The actual number of bytes read.
+ * @return        True if the complete tag value could be read in pResult else False.
+ */
+bd_bool_t BD_GetBlob( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index,
+                      char* pResult, bd_size_t bufLen, bd_size_t* pReadLen );
+
+/**
+ * Gets an IPv4 address from a BD.
+ *
+ * The IP address is returned as a 32 bits unsigned integer with the most
+ * significant byte first. E.g. 192.168.2.1 is stored as 0xC0A80201
+ *
+ * @param[in]     pCtx      The context from which the IP address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read IP address.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetIPv4( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult );
+
+/**
+ * Gets an Ethernet MAC address from a BD.
+ *
+ * @param[in]     pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read MAC address.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetMAC( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint8_t pResult[6] );
+
+/**
+ * Gets a partition entry from a BD.
+ *
+ * @param[in,out] pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the partition entry
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetPartition( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry* pResult );
+
+/**
+ * Gets a partition64 entry from a BD.
+ *
+ * @param[in,out] pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the partition entry
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetPartition64( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry64* pResult );
+
+
+#ifdef BD_CONF_HAS_HASH
+
+/**
+ * Verifies the SHA1-HMAC checksum.
+ *
+ * The checksum is computed with the specified key over the area defined
+ * by the hash tag. The key must match the one used to generate the descriptor.
+ *
+ * @param[in]     pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[in]     pKey      Pointer to key for HMAC initialization.
+ * @param[in]     keyLen    Size of the key.
+ * @return        True if the protected data is unmodified. False in any other case.
+ */
+bd_bool_t BD_VerifySha1Hmac( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, const void* pKey, bd_size_t keyLen );
+
+#endif
+
+
+#ifdef BD_CONF_UNIT_TESTS
+
+/**
+ * Runs unit tests
+ *
+ * If an error occurs an assert is triggered
+ */
+void BD_UnitTest(void);
+
+#endif /* BD_CONF_UNIT_TESTS */
+
+
+#ifdef __cplusplus
+} /*end extern c*/
+#endif
+
+#endif /* _BDPARSER_H */
+

board/nm/common/board_descriptor.c

@@ -0,0 +1,297 @@
+/******************************************************************************
+ * (c) COPYRIGHT 2010 by NetModule AG, Switzerland.  All rights reserved.
+ *
+ * The program(s) may only be used and/or copied with the written permission
+ * from NetModule AG or in accordance with the terms and conditions stipulated
+ * in the agreement contract under which the program(s) have been supplied.
+ *
+ * PACKAGE : NetBox HW08
+ *
+ * ABSTRACT:
+ *  Implements functions for settings
+ *
+ * HISTORY:
+ *  Date      Author       Description
+ *  20100421  SMA          created
+ *  20100903  rs           reading carrier board descriptor from EEPROM at 54.
+ *                         code cleanup (tabs/indentation)
+ *  20110211  rs           partition table handling
+ *
+ *****************************************************************************/
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#include "bdparser.h"		/* tlv parser */
+
+#define MAX_PARTITION_ENTRIES			4
+
+static const BD_Context		*bdctx_list;		/* The board descriptor context */
+static size_t				bdctx_count = 0;
+
+void bd_register_context_list(const BD_Context *list, size_t count) {
+	bdctx_list = list;
+	bdctx_count = count;
+}
+
+int bd_get_context(BD_Context *bdctx, uint32_t i2caddress, uint32_t offset)
+{
+	bd_bool_t	rc;
+	uint8_t		bdHeader[8];
+	void*		pBdData = NULL;
+	/* Read header bytes from beginning of EEPROM */
+	if (i2c_read( i2caddress, offset, 2, bdHeader, BD_HEADER_LENGTH )) {
+		debug("%s() Can't read BD header from EEPROM\n", __func__);
+		goto exit1;
+	}
+
+	/* Check whether this is a valid board descriptor (or empty EEPROM) */
+	rc = BD_CheckHeader( bdctx, bdHeader );
+	if (!rc) {
+		debug("%s() No valid board descriptor found\n", __func__);
+		goto exit1;
+	}
+
+	/* Allocate memory for descriptor data and .. */
+	pBdData = malloc( bdctx->size );
+	if ( pBdData == NULL ) {
+		debug("%s() Can't allocate %d bytes\n", __func__, bdctx->size);
+		goto exit1;
+	}
+
+	/* .. read data from EEPROM */
+	if (i2c_read(i2caddress, offset+BD_HEADER_LENGTH, 2, pBdData, bdctx->size)) {
+		debug("%s() Can't read data from EEPROM\n", __func__);
+		goto exit1;
+	}
+
+	/*
+	 * Import data into board descriptor context
+	 */
+	rc = BD_ImportData( bdctx, pBdData );
+	if (!rc) {
+		debug("%s() Invalid board descriptor data\n", __func__);
+		goto exit1;
+	}
+
+	return 0;
+
+exit1:
+	if (pBdData != NULL)
+	{
+		free(pBdData);
+		pBdData = NULL;
+	}
+
+	return -1;
+}
+
+static bd_bool_t _get_string(bd_uint16_t tag, bd_uint_t index, char* pResult, bd_size_t bufLen ) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetString(&bdctx_list[i], tag, index, pResult, bufLen)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_mac( bd_uint16_t tag, bd_uint_t index, bd_uint8_t pResult[6] ) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetMAC(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint8( bd_uint16_t tag, bd_uint_t index, bd_uint8_t* pResult ) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt8(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint16( bd_uint16_t tag, bd_uint_t index, bd_uint16_t* pResult ) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt16(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint32( bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult ) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt32(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_partition64( bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry64 *pResult) {
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetPartition64(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+int bd_get_prodname(char *prodname, size_t len)
+{
+	if ( !_get_string( BD_Prod_Name, 0, prodname, len) ) {
+		debug("%s() Product name not found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+void bd_get_hw_version(int* ver, int* rev)
+{
+	static uint8_t hwver;
+	static uint8_t hwrev;
+
+	if ( !_get_uint8( BD_Hw_Ver, 0, &hwver) )
+		debug("%s() no Hw Version found\n", __func__);
+
+	if ( !_get_uint8( BD_Hw_Rel, 0, &hwrev) )
+		debug("%s() no Hw Release found\n", __func__);
+
+	*ver = hwver;
+	*rev = hwrev;
+}
+
+int bd_get_mac(int index, uint8_t *macaddr, size_t len)
+{
+	if (len != 6) {
+		debug("macaddr size must be 6 (is %d)", len);
+		return -1;
+	}
+
+	/* MAC address */
+	if ( !_get_mac( BD_Eth_Mac, index, macaddr) ) {
+		debug("%s() MAC addresss %d not found\n", __func__, index);
+		return -1;
+	}
+
+	return 0;
+}
+
+u32 bd_get_fpgainfo(void)
+{
+	uint32_t fpgainfo = 0xFFFFFFFF;
+
+	if ( !_get_uint32( BD_Fpga_Info, 0, &fpgainfo) )
+		debug("%s() no Fpga Info found\n", __func__);
+
+	return fpgainfo;
+}
+
+int bd_get_pd_module(int slot, char *config, size_t len)
+{
+	if ( !_get_string(BD_Pd_Module0 + slot, 0, config, len) ) {
+		debug("%s() could not read module configuration on slot %d\n",
+				__func__, slot);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_sim_config(char* simconfig, size_t len)
+{
+	if (!_get_string(BD_Pd_Sim, 0, simconfig, len)) {
+		debug("%s() No valid SIM Config found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_devicetree(char* devicetreename, size_t len)
+{
+	if (!_get_string(PD_Dev_Tree, 0, devicetreename, len)) {
+		debug("%s() No valid Devicetree name found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_shield(int shieldnr)
+{
+	bd_uint16_t shield = 0;
+
+	if (!_get_uint16(PD_Shield, shieldnr, &shield) ) {
+		debug("%s() no shield populated\n", __func__);
+		return -1;
+	}
+
+	return shield;
+}
+
+static u8 try_partition_read(void)
+{
+	BD_PartitionEntry64 partition;
+	int i;
+	int rc;
+	int partition_count = 0;
+	int boot_partition = 0;
+
+	for (i = 0; i < MAX_PARTITION_ENTRIES; i++)
+	{
+		rc = _get_partition64(BD_Partition64, i, &partition);
+		if (rc) {
+			partition_count++;
+			if (((partition.flags & BD_Partition_Flags_Active) != 0) &&
+					(i > 0)) {
+				boot_partition = i;
+			}
+		}
+	}
+
+	if (partition_count < 1)
+	{
+		printf("ERROR: Too few partitions defined, taking default 0\n");
+	}
+
+	return boot_partition;
+
+}
+
+int bd_get_boot_partition(void)
+{
+	u8 boot_part;
+
+	/* If we have a new Bootpartition entry take this as boot part */
+	if ( _get_uint8( BD_BootPart, 0, &boot_part) ) {
+		if (boot_part >= 0 && boot_part <= 1) {
+			return boot_part;
+		}
+	}
+
+	/* If we not have a Bootpartition entry, perhaps we have a partition table */
+	return try_partition_read();
+}

board/nm/common/board_descriptor.h

@@ -0,0 +1,22 @@
+/*
+ * Library to support early TI EVM EEPROM handling
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_DESCRIPTOR_H
+#define __BOARD_DESCRIPTOR_H
+
+int bd_read(int bus_addr, int dev_addr);
+u8 bd_get_boot_partition(void);
+int bd_get_mac(uint index, u8 *mac_address, u32 len);
+int bd_get_hw_version(int* pVer, int* pRev);
+int bd_get_devicetree(char* devicetreename, size_t len);
+int bd_get_context(BD_Context *bdctx, uint32_t i2caddress, uint32_t offset);
+void bd_register_context_list(const BD_Context *list, size_t count);
+u8 bd_get_boot_partition(void);
+int bd_get_shield(int shieldnr);
+
+#endif	/* __BOARD_DESCRIPTOR_H */

board/nm/netbird/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NETBIRD
+
+config SYS_BOARD
+        default "netbird"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_netbird"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 1
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/netbird/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o

board/nm/netbird/board.c

@@ -0,0 +1,575 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <serial.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65218.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "../common/bdparser.h"
+#include "../common/board_descriptor.h"
+#include "board.h"
+#include <console.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+
+#define NETBIRD_GPIO_RST_PHY_N	GPIO_TO_PIN(0, 16)
+#define NETBIRD_GPIO_PWR_GSM	GPIO_TO_PIN(1, 22)
+#define NETBIRD_GPIO_RST_GSM	GPIO_TO_PIN(1, 24)
+#define NETBIRD_GPIO_WLAN_EN	GPIO_TO_PIN(3, 10)
+#define NETBIRD_GPIO_BT_EN		GPIO_TO_PIN(3, 4)
+#define NETBIRD_GPIO_EN_GPS_ANT	GPIO_TO_PIN(2, 24)
+#define NETBIRD_GPIO_LED_A		GPIO_TO_PIN(1, 14)
+#define NETBIRD_GPIO_LED_B		GPIO_TO_PIN(1, 15)
+#define NETBIRD_GPIO_RESET_BUTTON	GPIO_TO_PIN(1, 13)
+
+#define DDR3_CLOCK_FREQUENCY (400)
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+
+#define BD_EEPROM_ADDR			(0x50)	/* CPU BD EEPROM (8kByte) is at 50 (A0) */
+#define BD_ADDRESS				(0x0000)  /* Board descriptor at beginning of EEPROM */
+#define PD_ADDRESS				(0x0200)  /* Product descriptor */
+#define PARTITION_ADDRESS		(0x0600)  /* Partition Table */
+
+static BD_Context   bdctx[3];		/* The descriptor context */
+
+static int _bd_init(void)
+{
+	if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
+		printf("%s() no valid bd found\n", __func__);
+		return -1;
+	}
+
+	if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
+		printf("%s() no valid pd found (legacy support)\n", __func__);
+	}
+
+	if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
+		printf("%s() no valid partition table found\n", __func__);
+	}
+
+	bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
+    return 0;
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static inline int __maybe_unused read_eeprom(void)
+{
+    return _bd_init();
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &eserial1_device;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_netbird_data = {
+	/* Ratios were optimized by DDR3 training software from TI */
+	.datardsratio0 = 0x37,
+	.datawdsratio0 = 0x42,
+	.datafwsratio0 = 0x98,
+	.datawrsratio0 = 0x7a,
+};
+
+static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_netbird_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = 0x61A,	/* 32ms > 85°C */
+	.sdram_tim1 = 0x0AAAE51B,
+	.sdram_tim2 = 0x246B7FDA,
+	.sdram_tim3 = 0x50FFE67F,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_relocate_spec();
+	if (getenv_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+struct dpll_params dpll_ddr_nbhw16= {
+		DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CPU speed to 600 MHZ */
+	dpll_mpu_opp100.m = MPUPLL_M_600;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Clear th PFM Flag on DCDC4 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_DCDC4, 0x00, 0x80)) {
+		puts ("tps65218_reg_write failure\n");
+	};
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	dpll_ddr_nbhw16.n = (get_osclk() / 1000000) - 1;
+	return &dpll_ddr_nbhw16;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+
+const struct ctrl_ioregs ioregs_netbird = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+	config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
+		   &ddr3_netbird_data,
+		   &ddr3_netbird_cmd_ctrl_data,
+		   &ddr3_netbird_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+static void request_and_set_gpio(int gpio, char *name, int value)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, value);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLEAR_GPIO(N)	request_and_set_gpio(N, #N, 0);
+
+
+int check_reset_button(void)
+{
+	int counter = 0;
+	int ret;
+
+	ret = gpio_request(NETBIRD_GPIO_RESET_BUTTON, "reset button");
+	if (ret < 0) {
+		printf("Unable to request reset button gpio\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_RESET_BUTTON);
+	if (ret < 0) {
+		printf("Unable to set reset button as input\n");
+		return -1;
+	}
+
+	/* Check if reset button is pressed for at least 3 seconds */
+	do {
+		if (gpio_get_value(NETBIRD_GPIO_RESET_BUTTON) != 0)  break;
+		udelay(100000);  /* 100ms */
+		counter++;
+
+		if (counter==30) {/* Indicate factory reset threshold */
+			/* let LED blink up once */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		} else if (counter==150) { /* Indicate recovery boot threshold */
+			/* let LED blink up twice */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		}
+	} while (counter<150);
+
+	if (counter < 30) return 0; /* Don't do anything for duration < 3s */
+
+	if (counter < 150) /* Do factory reset for duration between 3s and 15s */
+	{
+		char new_bootargs[512];
+		char *bootargs = getenv("bootargs");
+
+		if (bootargs==0) bootargs="";
+
+		printf("Do factory reset during boot...\n");
+
+		strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
+		strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
+
+		setenv("bootargs", new_bootargs);
+
+		printf("bootargs = %s\n", new_bootargs);
+
+		return 1;
+	} else {	/* Boot into recovery for duration > 15s */
+
+		/* set consoledev to external port */
+		setenv("consoledev", "ttyO0");
+
+		printf("Booting recovery image...\n");
+
+		/* Set bootcmd to run recovery */
+		setenv("bootcmd", "run recovery");
+
+		return 0;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NB_TEST
+/*
+ * Perform a hardware reset test. The complete test loops until
+ * interrupted by ctrl-c or by pressed the RESET button.
+ */
+int do_hwreset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 gpio_cpu_value = 0x00000000;
+
+	printf("  Press RESET button in hardware reset the board.\n");
+
+	while (gpio_cpu_value == 0) {
+		gpio_cpu_value = (gpio_get_value(NETBIRD_GPIO_RESET_BUTTON) == 0) ? 1 : 0;
+
+		printf("RESET_BTN = %d\n",gpio_cpu_value);
+		if (ctrlc()) {
+			putc ('\n');
+			return 1;
+		}
+		udelay(20*1000);
+	}
+	return 1;
+}
+#endif /* CONFIG_CMD_NB_TEST */
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_RST_GSM);
+	udelay(10000);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_PWR_GSM);
+	mdelay(1200);
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 0);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_LED_A);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_LED_B);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_PHY_N);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_WLAN_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_BT_EN);
+	/* There are two funcions on the same mux mode for MMC2_DAT7 we want
+	 * to use RMII2_CRS_DV so we need to set SMA2 Register to 1
+	 * See SPRS717J site 49 (10)*/
+	#define SMA2_REGISTER (CTRL_BASE + 0x1320)
+	writel(0x01, SMA2_REGISTER); /* Select RMII2_CRS_DV instead of MMC2_DAT7 */
+
+	printf("OSC: %lu Hz\n", get_osclk());
+
+	return 0;
+}
+#if !defined(CONFIG_SPL_BUILD)
+
+static void set_devicetree_name(void)
+{
+	char devicetreename[64];
+	/* add hardware versions to environment */
+	if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
+		printf("Devicetree name not found, use legacy name\n");
+		strcpy(devicetreename, "am335x-nbhw16.dtb");
+	}
+
+	setenv("fdt_image", devicetreename);
+}
+
+static void get_hw_version(void)
+{
+	int hw_ver, hw_rev;
+	char hw_versions[16];
+	char new_env[256];
+
+	/* add hardware versions to environment */
+	bd_get_hw_version(&hw_ver, &hw_rev);
+	printf("HW16:  V%d.%d\n", hw_ver, hw_rev);
+	snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
+	snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
+	setenv("add_version_bootargs", new_env);
+}
+
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	int boot_partition;
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	/* add active root partition to environment */
+	boot_partition = bd_get_boot_partition();
+	if (boot_partition > 1) {
+		boot_partition = 0;
+	}
+
+	/* mmcblk1p1 => root0, mmcblk1p2 => root1 so +1 */
+	setenv_ulong("root_part", boot_partition + 1);
+
+	check_reset_button();
+
+	get_hw_version();
+
+	set_devicetree_name();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	int rc;
+	char *name = NULL;
+
+	set_board_info_env(name);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
+static void set_mac_address(int index, uchar mac[6])
+{
+	/* Then take mac from bd */
+	if (is_valid_ethaddr(mac)) {
+		eth_setenv_enetaddr_by_index("eth", index, mac);
+	}
+	else {
+		printf("Trying to set invalid MAC address");
+	}
+}
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr0[6] = {02,00,00,00,00,01};
+	uint8_t mac_addr1[6] = {02,00,00,00,00,02};
+	__maybe_unused struct ti_am_eeprom *header;
+
+#if !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+	cpsw_data.mdio_div = 0x3E;
+
+	bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
+	set_mac_address(0, mac_addr0);
+
+	bd_get_mac(1, mac_addr1, sizeof(mac_addr1));
+	set_mac_address(1, mac_addr1);
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[0].phy_addr = 0;
+	cpsw_slaves[1].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr0))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif

board/nm/netbird/board.h

@@ -0,0 +1,27 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif

board/nm/netbird/mux.c

@@ -0,0 +1,227 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+
+
+static struct module_pin_mux uart0_netbird_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_netbird_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd.uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},				/* (D15) uart1_txd.uart1_txd */
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D18) uart1_ctsn.uart1_ctsn */
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN | PULLUP_EN)},				/* (D17) uart1_rtsn.uart1_rtsn */
+	{-1},
+};
+
+static struct module_pin_mux rmii0_netbird_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS },			/* MII1_TXEN */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS },			/* MII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS },			/* MII1_TXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE },	/* MII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE },	/* MII1_RXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},	/* RMII1_REFCLK */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS },	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE }, /* MDIO_DATA */
+	{OFFSET(xdma_event_intr0), MODE(3) }, /* CLK_OUT1 for MDIO (design option) */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_netbird_pin_mux[] = {
+	{OFFSET(gpmc_a9), MODE(3) | PULLUDDIS | RXACTIVE},		/* MII2_CRS */
+	{OFFSET(gpmc_wpn), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII2_RXERR */
+	{OFFSET(gpmc_a0), MODE(3) | PULLUDDIS},			/* MII2_TXEN */
+	{OFFSET(gpmc_a5), MODE(3) | PULLUDDIS},			/* MII2_TXD0 */
+	{OFFSET(gpmc_a4), MODE(3) | PULLUDDIS},			/* MII2_TXD1 */
+	{OFFSET(gpmc_a11), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(gpmc_a10), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_col), MODE(1) | PULLUDDIS | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux gpio_netbird_pin_mux[] = {
+	/* Bank 0 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */  /* PWM */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},	/* (J18) gmii1_txd3.gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* (U12) gpmc_ad11.gpio0[27] */  /* RST_EXT~ */
+	/* Bank 1 */
+	{OFFSET(gpmc_ad13), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R12) gpmc_ad13.gpio1[13] */  /* BUTTON */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},	/* (V13) gpmc_ad14.gpio1[14] */  /* LED_A */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)},	/* (U13) gpmc_ad15.gpio1[15] */  /* LED_B */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* (U15) gpmc_a6.gpio1[22] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},	/* (V16) gpmc_a8.gpio1[24] */  /* RST_GSM~ */
+	/* Bank 2 */
+	{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)},	/* (V5) lcd_pclk.gpio2[24] */  /* EN_GPS_ANT */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[9] */  /* SYSBOOT */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[10] */  /* SYSBOOT */
+	/* Bank 3 */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (J17) gmii1_rxdv.gpio3[4] */  /* BT_EN */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (K18) gmii1_txclk.gpio3[9] */  /* WLAN_IRQ */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (L18) gmii1_rxclk.gpio3[10] */  /* WLAN_EN */
+	{-1},
+};
+
+static struct module_pin_mux usb_netbird_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN | PULLDOWN_EN)},	/* (F16) USB0_DRVVBUS.USB0_DRVVBUS */  /* PWM */
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F15) USB1_DRVVBUS.USB1_DRVVBUS */  /* RST_PHY~ */
+	{-1},
+};
+
+static struct module_pin_mux unused_netbird_pin_mux[] = {
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT6 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT7 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT10 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT11 is not used bulldown active, receiver disabled */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_netbird_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_netbird_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles.  These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE	0x0
+#define PROFILE_0	(1 << 0)
+#define PROFILE_1	(1 << 1)
+#define PROFILE_2	(1 << 2)
+#define PROFILE_3	(1 << 3)
+#define PROFILE_4	(1 << 4)
+#define PROFILE_5	(1 << 5)
+#define PROFILE_6	(1 << 6)
+#define PROFILE_7	(1 << 7)
+#define PROFILE_MASK	0x7
+#define PROFILE_ALL	0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR	0x35
+#define CFG_REG		0x10
+
+void enable_board_pin_mux(void)
+{
+	/* Netbird board */
+	configure_module_pin_mux(gpio_netbird_pin_mux);
+	configure_module_pin_mux(rmii0_netbird_pin_mux);
+	configure_module_pin_mux(rmii1_netbird_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(unused_netbird_pin_mux);
+}

board/nm/netbird/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/netbird/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/netbird_v2/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NETBIRD_V2
+
+config SYS_BOARD
+        default "netbird_v2"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_netbird_v2"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/netbird_v2/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o shield.o shield_can.o shield_comio.o shield_gnsscan.o fileaccess.o

board/nm/netbird_v2/board.c

@@ -0,0 +1,846 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <serial.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65218.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "../common/bdparser.h"
+#include "../common/board_descriptor.h"
+#include "board.h"
+#include "shield.h"
+#include "shield_can.h"
+#include "shield_comio.h"
+#include "shield_gnsscan.h"
+#include "fileaccess.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+
+#define NETBIRD_GPIO_RST_PHY_N	GPIO_TO_PIN(0, 16)
+#define NETBIRD_GPIO_PWR_GSM	GPIO_TO_PIN(1, 21)
+#define NETBIRD_GPIO_SUPPLY_GSM	GPIO_TO_PIN(0, 31)
+#define NETBIRD_GPIO_RST_GSM	GPIO_TO_PIN(1, 25)
+#define NETBIRD_GPIO_WLAN_EN	GPIO_TO_PIN(3, 10)
+#define NETBIRD_GPIO_BT_EN		GPIO_TO_PIN(3, 4)
+#define NETBIRD_GPIO_EN_GPS_ANT	GPIO_TO_PIN(2, 24)
+#define NETBIRD_GPIO_LED_A		GPIO_TO_PIN(1, 14)
+#define NETBIRD_GPIO_LED_B		GPIO_TO_PIN(1, 15)
+#define NETBIRD_GPIO_RESET_BUTTON	GPIO_TO_PIN(0, 2)
+#define NETBIRD_GPIO_USB_PWR_EN		GPIO_TO_PIN(1, 27)
+#define NETBIRD_GPIO_USB_PWR_EN_2	GPIO_TO_PIN(2, 4) // On new version this gpio is used
+
+#define DDR3_CLOCK_FREQUENCY (400)
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+
+#define BD_EEPROM_ADDR			(0x50)	/* CPU BD EEPROM (8kByte) is at 50 (A0) */
+#define BD_ADDRESS				(0x0000)  /* Board descriptor at beginning of EEPROM */
+#define PD_ADDRESS				(0x0200)  /* Product descriptor */
+#define PARTITION_ADDRESS		(0x0600)  /* Partition Table */
+
+static BD_Context   bdctx[3];		/* The descriptor context */
+
+#define SHIELD_COM_IO	0
+#define SHIELD_DUALCAN	1
+#define SHIELD_GNSSCAN	2
+
+static int _bd_init(void)
+{
+	if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
+		printf("%s() no valid bd found\n", __func__);
+		return -1;
+	}
+
+	if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
+		printf("%s() no valid pd found (legacy support)\n", __func__);
+	}
+
+	if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
+		printf("%s() no valid partition table found\n", __func__);
+	}
+
+	bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
+	return 0;
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static inline int __maybe_unused read_eeprom(void)
+{
+	return _bd_init();
+}
+
+struct serial_device *default_serial_console(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_UART) {
+		enable_uart0_pin_mux();
+		return &eserial1_device;
+	}
+	else {
+		return &eserial2_device;
+	}
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_netbird_data = {
+	/* Ratios were optimized by DDR3 training software from TI */
+	.datardsratio0 = 0x39,
+	.datawdsratio0 = 0x3f,
+	.datafwsratio0 = 0x98,
+	.datawrsratio0 = 0x7d,
+};
+
+static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_netbird_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = 0x61A,	/* 32ms > 85°C */
+	.sdram_tim1 = 0x0AAAE51B,
+	.sdram_tim2 = 0x246B7FDA,
+	.sdram_tim3 = 0x50FFE67F,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_relocate_spec();
+	if (getenv_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+struct dpll_params dpll_ddr_nbhw16= {
+		DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CPU speed to 600 MHZ */
+	dpll_mpu_opp100.m = MPUPLL_M_600;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Clear th PFM Flag on DCDC4 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_DCDC4, 0x00, 0x80)) {
+		puts ("tps65218_reg_write failure (DCDC4 clear PFM Flag)\n");
+	};
+
+	/* Disable DCDC2 because it is not used and could make noise */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE1, 0, 0x02)) {
+		puts ("tps65218_reg_write failure (DCDC2 disable)\n");
+	};
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	dpll_ddr_nbhw16.n = (get_osclk() / 1000000) - 1;
+	return &dpll_ddr_nbhw16;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_disabled_pin_mux();
+	enable_uart1_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+
+const struct ctrl_ioregs ioregs_netbird = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+	config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
+		   &ddr3_netbird_data,
+		   &ddr3_netbird_cmd_ctrl_data,
+		   &ddr3_netbird_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+static void request_and_set_gpio(int gpio, char *name, int value)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, value);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLEAR_GPIO(N)	request_and_set_gpio(N, #N, 0);
+
+
+int check_reset_button(void)
+{
+	int counter = 0;
+	int ret;
+
+	ret = gpio_request(NETBIRD_GPIO_RESET_BUTTON, "reset button");
+	if (ret < 0) {
+		printf("Unable to request reset button gpio\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_RESET_BUTTON);
+	if (ret < 0) {
+		printf("Unable to set reset button as input\n");
+		return -1;
+	}
+
+	/* Check if reset button is pressed for at least 2 seconds ≃ ~5s */
+	do {
+		if (gpio_get_value(NETBIRD_GPIO_RESET_BUTTON) != 0)  break;
+		udelay(100000);  /* 100ms */
+		counter++;
+
+		if (counter==20) {/* Indicate factory reset threshold */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			/* let LED blink up once */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		} else if (counter==120) { /* Indicate recovery boot threshold */
+			/* let LED blink up twice */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		}
+	} while (counter<120);
+
+	if (counter < 20) return 0; /* Don't do anything for duration < 2s */
+
+	if (counter < 120) /* Do factory reset for duration between ~5s and ~15s */
+	{
+		char new_bootargs[512];
+		char *bootargs = getenv("bootargs");
+
+		if (bootargs==0) bootargs="";
+
+		printf("Do factory reset during boot...\n");
+
+		strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
+		strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
+
+		setenv("bootargs", new_bootargs);
+
+		printf("bootargs = %s\n", new_bootargs);
+
+		return 1;
+	} else {	/* Boot into recovery for duration > 15s */
+		/* set consoledev to external port */
+		setenv("consoledev", "ttyS1");
+
+		printf("Booting recovery image...\n");
+
+		/* Set bootcmd to run recovery */
+		setenv("bootcmd", "run recovery");
+
+		return 0;
+	}
+	return 0;
+}
+
+static void enable_ext_usb(void)
+{
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_USB_PWR_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_USB_PWR_EN_2);
+	/* Disable LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE2, 0x00, 0x04)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+
+	/* Discharge LS2 to have proper 0V at the output */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG3, 0x02, 0x02)) {
+		puts ("tps65218_reg_write failure (LS2 discharge)\n");
+	};
+
+	mdelay(10);
+
+	gpio_set_value(NETBIRD_GPIO_USB_PWR_EN, 1);
+	gpio_set_value(NETBIRD_GPIO_USB_PWR_EN_2, 1);
+
+	mdelay(50);
+
+	/* Disable discharge LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG3, 0x00, 0x02)) {
+		puts ("tps65218_reg_write failure (LS2 discharge)\n");
+	};
+
+	/* Configure 500mA on LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG2, 0x02, 0x03)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+
+	/* Enable LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE2, 0x04, 0x04)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+
+	/* Remove power, and make sure reset is set once */
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_SUPPLY_GSM);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_GSM);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_PWR_GSM);
+	mdelay(20);
+	/* Enable gsm supply */
+	gpio_set_value(NETBIRD_GPIO_SUPPLY_GSM, 1);
+	mdelay(20);
+	/* Take modem out of reset, we have to wait 300ms afterwards */
+	gpio_set_value(NETBIRD_GPIO_RST_GSM, 0);
+	mdelay(300);
+	/* Do power up sequence, this modem has a special power up sequence
+	 * where we have to pull PWR for > 1s but < 7s (see manual) */
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 1);
+	mdelay(1200);
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 0);
+
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_LED_A);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_LED_B);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_PHY_N);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_WLAN_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_BT_EN);
+
+	/* There are two funcions on the same mux mode for MMC2_DAT7 we want
+	 * to use RMII2_CRS_DV so we need to set SMA2 Register to 1
+	 * See SPRS717J site 49 (10)*/
+	#define SMA2_REGISTER (CTRL_BASE + 0x1320)
+	writel(0x01, SMA2_REGISTER); /* Select RMII2_CRS_DV instead of MMC2_DAT7 */
+
+	enable_ext_usb();
+
+	printf("OSC:   %lu Hz\n", get_osclk());
+
+	return 0;
+}
+
+/* Enable the ecap2 pwm see siemens/pxm2 */
+static int enable_pwm(void)
+{
+#define PWM_TICKS	0xBEB
+#define PWM_DUTY	0x5F5
+#define AM33XX_ECAP2_BASE 0x48304100
+#define PWMSS2_BASE 0x48304000
+	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS2_BASE;
+	struct pwmss_ecap_regs *ecap;
+	int ticks = PWM_TICKS;
+	int duty = PWM_DUTY;
+
+	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP2_BASE;
+	/* enable clock */
+	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
+	/* TimeStamp Counter register */
+	writel(0x0, &ecap->ctrphs);
+
+	setbits_le16(&ecap->ecctl2,
+			 (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK));
+
+	/* config period */
+	writel(ticks - 1, &ecap->cap3);
+	writel(ticks - 1, &ecap->cap1);
+	/* config duty */
+	writel(duty, &ecap->cap2);
+	writel(duty, &ecap->cap4);
+	/* start */
+	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
+	return 0;
+}
+
+/* Enable the input clock for ecap2 and then enable the pwm */
+static void enable_wlan_clock(void)
+{
+	struct cm_perpll *const cmper = (struct cm_perpll*)CM_PER;
+	struct ctrl_dev *const cdev= (struct ctrl_dev*)CTRL_DEVICE_BASE;
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_nmspecific[] = {
+		&cmper->epwmss2clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_nmspecific, 1);
+
+	/* Enable timebase clock for pwmss2 */
+	writel(0x04, &cdev->pwmssctrl);
+
+	enable_pwm();
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+void set_console(void)
+{
+	char *defaultconsole = getenv("defaultconsole");
+	char buf[20];
+	int i;
+	int shield_id = bd_get_shield(0);
+
+	if (defaultconsole == 0) {
+		/* Use the default console */
+		setenv("defaultconsole", "ttyS1");
+	}
+
+	/* Don't allow changing to ttyS0 because ttyS0 is not available in the
+	 * kernel if no comio shield is available */
+	if (shield_id != SHIELD_COM_IO) {
+		return;
+	}
+	
+	/* With comio shield the defaultconsole should be ttyS0 and not ttyS1 */
+	setenv("defaultconsole", "ttyS0");
+
+	/* If consoledev file is present, take the tty defined in it as console */
+	if (read_file("/root/boot/consoledev",buf, sizeof(buf)) > 3) {
+		if (strstr(buf, "tty") == buf) {
+			buf[sizeof(buf)-1] = 0;
+			for (i=0; i<sizeof(buf); i++) {
+				if (buf[i]<=' ') {
+					buf[i] = 0;
+					break;
+				}
+			}
+			setenv("defaultconsole", buf);
+		}
+	}
+}
+
+static void set_devicetree_name(void)
+{
+	char devicetreename[64];
+	/* add hardware versions to environment */
+	if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
+		printf("Devicetree name not found, use legacy name\n");
+		strcpy(devicetreename, "am335x-nbhw16-prod2.dtb");
+	}
+
+	setenv("fdt_image", devicetreename);
+}
+
+static void get_hw_version(void)
+{
+	int hw_ver, hw_rev;
+	char hw_versions[16];
+	char new_env[256];
+
+	/* add hardware versions to environment */
+	bd_get_hw_version(&hw_ver, &hw_rev);
+	printf("HW16:  V%d.%d\n", hw_ver, hw_rev);
+	snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
+	snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
+	setenv("add_version_bootargs", new_env);
+}
+
+static void check_fct(void)
+{
+	/* If probe fails we are sure no eeprom is connected */
+	if (i2c_probe(0x51) == 0) {
+		printf("Entering fct mode\n");
+		setenv ("bootcmd", "");
+	}
+}
+
+
+static void set_fdtshieldcmd(const char *fdt_cmd)
+{
+	setenv("fdtshieldcmd", fdt_cmd);
+}
+
+struct shield_command {
+	int shield_id;
+	const char *name;
+	const char *default_shieldcmd;
+	const char *fdtshieldcmd;
+	void (*init)(void);
+};
+
+static struct shield_command known_shield_commands[] = {
+	{
+		SHIELD_COM_IO,
+		"comio",
+		"shield comio mode rs232",
+		"fdt get value serial0 /aliases serial0;" \
+		"fdt get value dio0 /aliases dio0;" \
+		"fdt set $serial0 status okay;" \
+		"fdt set $dio0 status okay;",
+		comio_shield_init
+	},
+	{
+		SHIELD_DUALCAN,
+		"dualcan",
+		"shield dualcan termination off off",
+		"fdt get value can0 /aliases d_can0;" \
+		"fdt get value can1 /aliases d_can1;" \
+		"fdt set $can0 status okay;" \
+		"fdt set $can1 status okay;",
+		can_shield_init
+	},
+	{
+		SHIELD_GNSSCAN,
+		"gnsscan",
+		"shield gnsscan termination off",
+		"fdt get value serial0 /aliases serial0;" \
+		"fdt get value can1 /aliases d_can1;" \
+		"fdt set $serial0 status okay;" \
+		"fdt set $can1 status okay;" \
+		/* fix uart0 pinctrl: */ \
+		"fdt get value dt_path /aliases uart0_pins_gnss_can;" \
+		"fdt get value dt_phandle $dt_path phandle;" \
+		"fdt get value dt_path /aliases serial0;" \
+		"fdt set $dt_path pinctrl-0 <$dt_phandle>;" \
+		,
+		gnsscan_shield_init
+	},
+};
+
+static const struct shield_command* get_shield_command(int shield_id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(known_shield_commands); i++) {
+		if (known_shield_commands[i].shield_id == shield_id) {
+			return &known_shield_commands[i];
+		}
+	}
+
+	return NULL;
+}
+
+static void shield_config(void)
+{
+#define MAX_SHIELD_CMD_LEN 128
+	char shieldcmd_linux[MAX_SHIELD_CMD_LEN];
+	const char *shieldcmd;
+	const struct shield_command *cmd;
+	int len;
+
+	int shield_id = bd_get_shield(0);
+	if (shield_id < 0) {
+		debug("No shield found in bd\n");
+		return;
+	}
+
+	cmd = get_shield_command(shield_id);
+	if (cmd == NULL) {
+		printf ("Unknown shield id %d\n", shield_id);
+		return;
+	}
+
+	printf("Shield: %s\n", cmd->name);
+
+	cmd->init();
+	shieldcmd = cmd->default_shieldcmd;
+
+	/* If a shield configuration set by linux take it without bd check, we asume that Linux knows
+	 * what to do. */
+	len = read_file("/root/boot/shieldcmd", shieldcmd_linux, MAX_SHIELD_CMD_LEN);
+	if (len > 0) {
+		debug("Shield command found in file, using it\n");
+		shieldcmd = shieldcmd_linux;
+	}
+
+	setenv("shieldcmd", shieldcmd);
+
+	set_fdtshieldcmd(cmd->fdtshieldcmd);
+}
+
+static void shield_init(void)
+{
+	shield_config();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	int boot_partition;
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	/* add active root partition to environment */
+	boot_partition = bd_get_boot_partition();
+	if (boot_partition > 1) {
+		boot_partition = 0;
+	}
+
+	/* mmcblk1p1 => root0, mmcblk1p2 => root1 so +1 */
+	setenv_ulong("root_part", boot_partition + 1);
+
+	check_reset_button();
+
+	get_hw_version();
+
+	set_devicetree_name();
+
+	set_console();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	int rc;
+	char *name = NULL;
+
+	set_board_info_env(name);
+#endif
+
+	enable_wlan_clock();
+
+#if !defined(CONFIG_SPL_BUILD)
+	shield_init();
+
+	check_fct();
+
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
+static void set_mac_address(int index, uchar mac[6])
+{
+	/* Then take mac from bd */
+	if (is_valid_ethaddr(mac)) {
+		eth_setenv_enetaddr_by_index("eth", index, mac);
+	}
+	else {
+		printf("Trying to set invalid MAC address");
+	}
+}
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr0[6] = {02,00,00,00,00,01};
+	__maybe_unused struct ti_am_eeprom *header;
+
+#if !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+	cpsw_data.mdio_div = 0x3E;
+
+	bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
+	set_mac_address(0, mac_addr0);
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[0].phy_addr = 0;
+	cpsw_slaves[1].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr0))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif

board/nm/netbird_v2/board.h

@@ -0,0 +1,30 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart0_disabled_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#endif

board/nm/netbird_v2/fileaccess.c

@@ -0,0 +1,43 @@
+#include <common.h>
+#include <fs.h>
+
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	/* File does not exist, do not print an error message */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}
+

board/nm/netbird_v2/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/netbird_v2/mux.c

@@ -0,0 +1,229 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux uart0_disabled_netbird_pin_mux[] = {
+    /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE )},	/* (E18) UART0_CTSN */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN )},			/* (E17) UART0_RTSN */
+	{-1},
+};
+
+static struct module_pin_mux uart0_netbird_pin_mux[] = {
+    /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux uart1_netbird_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd.uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* (D15) uart1_txd.uart1_txd */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux rmii1_netbird_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},		    /* (H17) mii1_crs.rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE},		    /* (J15) mii1_rxerr.rmii1_rxerr */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS },			    /* (J16) mii1_txen.rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS },			    /* (K17) mii1_txd0.rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS },			    /* (K16) mii1_txd1.rmii1_txd1 */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE },		    /* (M16) mii1_rxd0.rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE },		    /* (L15) mii1_rxd1.rmii1_rxd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},		    /* (H18) rmii1_refclk.rmii1_refclk */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS },			    /* (M18) mdio_clk.mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE },    /* (M17) mido_data.mdio_data */
+	{OFFSET(xdma_event_intr0), MODE(3) },				    /* (A15) xdma_event_intr0.clkout1 (25 MHz clk for MDIO) */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux gpio_netbird_pin_mux[] = {
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (A17) spi0_sclk.gpio0[2] */  /* BUTTON */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */  /* PWM */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},	/* (J18) gmii1_txd3.gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* (U12) gpmc_ad11.gpio0[27] */  /* RST_EXT~ */
+	/* Bank 1 */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},	/* (V13) gpmc_ad14.gpio1[14] */  /* LED_A */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)},	/* (U13) gpmc_ad15.gpio1[15] */  /* LED_B */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (V17) gpmc_a11.gpio1[27] */  /* USB_PWR_EN */
+	{OFFSET(gpmc_a9),   (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (U16) gpmc_a9.gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (U17) gpmc_csn3.gpio0[31] */  /* GSM_SUPP_EN */
+	{OFFSET(gpmc_a5),   (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (V15) gpmc_a5.gpio1[21] */  /* GSM_PWR_EN */
+	/* Bank 2 */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[9] */  /* SYSBOOT */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[10] */  /* SYSBOOT */
+	/* Bank 3 */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (J17) gmii1_rxdv.gpio3[4] */  /* BT_EN */
+	{OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},	/* (K18) gmii1_txclk.gpio3[9] */  /* WLAN_IRQ */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},	/* (L18) gmii1_rxclk.gpio3[10] */  /* WLAN_EN */
+	{OFFSET(mcasp0_ahclkr), (MODE(4) | PULLUDEN | PULLUP_EN)},	/* (C12) mcasp0_ahclkr.ecap2_in_pwm2_out */  /* WLAN_CLK */
+	{-1},
+};
+
+static struct module_pin_mux usb_netbird_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F16) USB0_DRVVBUS.USB0_DRVVBUS */  /* PWM */
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F15) USB1_DRVVBUS.USB1_DRVVBUS */  /* RST_PHY~ */
+	{-1},
+};
+
+static struct module_pin_mux unused_netbird_pin_mux[] = {
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT6 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT7 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT10 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT11 is not used bulldown active, receiver disabled */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_netbird_pin_mux);
+}
+
+void enable_uart0_disabled_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_netbird_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_netbird_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles.  These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE	0x0
+#define PROFILE_0	(1 << 0)
+#define PROFILE_1	(1 << 1)
+#define PROFILE_2	(1 << 2)
+#define PROFILE_3	(1 << 3)
+#define PROFILE_4	(1 << 4)
+#define PROFILE_5	(1 << 5)
+#define PROFILE_6	(1 << 6)
+#define PROFILE_7	(1 << 7)
+#define PROFILE_MASK	0x7
+#define PROFILE_ALL	0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR	0x35
+#define CFG_REG		0x10
+
+void enable_board_pin_mux(void)
+{
+	/* Netbird board */
+	configure_module_pin_mux(gpio_netbird_pin_mux);
+	configure_module_pin_mux(rmii1_netbird_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(unused_netbird_pin_mux);
+}

board/nm/netbird_v2/shield.c

@@ -0,0 +1,74 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define MAX_SHIELDS 16
+
+static struct shield_t *shields[MAX_SHIELDS];
+static int shield_count = 0;
+
+/* Perhaps this function shouldn't leave in shields.c? */
+int shield_gpio_request_as_input(unsigned int gpio, const char *label)
+{
+	int ret;
+
+ 	ret = gpio_request(gpio, label);
+	if ((ret < 0)) {
+		printf("Could not request shield slot %s gpio\n", label);
+		return -1;
+	}
+
+	ret = gpio_direction_input(gpio);
+	if ((ret < 0)) {
+		printf("Could not configure shield slot %s gpio as input\n", label);
+		return -1;
+	}
+
+	return 0;
+}
+
+void shield_register(struct shield_t *shield)
+{
+	if (shield_count >= MAX_SHIELDS) {
+		printf("Max shield count reached (%d), please increment MAX_SHIELDS\n", MAX_SHIELDS);
+		return;
+	}
+	shields[shield_count++] = shield;
+}
+
+int shield_set_mode(const char* shield_type, int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < shield_count; i++) {
+		if (strcmp(shield_type, shields[i]->name) == 0) {
+			return shields[i]->setmode(argv, argc);
+		}
+	}
+	printf("## Error: No %s shield installed\n", shield_type);
+	/* Do not return error, to not show usage (request by rs) */
+	return 0;
+}
+
+static int do_shieldmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		return -1;
+	}
+
+	return shield_set_mode(argv[1], argc - 2, &argv[2]);
+}
+
+U_BOOT_CMD(
+	shield,	6,	1,	do_shieldmode,
+	"Set the shield mode",
+	"shield dualcan termination on|off on|off\n"
+	"shield comio mode rs232|rs485 [termination on|off]\n"
+	"shield gnsscan termination on|off\n"
+);
+

board/nm/netbird_v2/shield.h

@@ -0,0 +1,21 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/shield.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Wed 31 May 2017 02:56:16 PM CEST \n
+ * 	Last Update:	Wed 31 May 2017 02:56:16 PM CEST
+ */
+#ifndef SHIELD_H
+#define SHIELD_H
+
+struct shield_t{
+    char name[64];
+    int (*setmode)(char * const argv[], int argc);
+};
+
+int shield_setmode(int mode);
+void shield_register(struct shield_t *shield);
+
+int shield_gpio_request_as_input(unsigned int gpio, const char *label);
+
+#endif // SHIELD_H

board/nm/netbird_v2/shield_can.c

@@ -0,0 +1,193 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LATCH GPIO_TO_PIN(0, 7)
+#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 10)
+#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 8)
+
+
+static int shield_slot_initialized = 0;
+
+
+static struct module_pin_mux can_shield_netbird_pin_mux_config[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* CAN1 tx */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* CAN0 tx */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* Latch EN */
+	{-1},
+};
+
+static struct module_pin_mux can_shield_netbird_pin_mux_final[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},	/* CAN1 tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},	/* CAN1 rx */
+	{OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)},	/* CAN0 rx */
+	{OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},			/* CAN0 tx */
+	{-1},
+};
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LATCH, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type dualcan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Configure shield pin muxing for configuration\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_config);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to high\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LATCH, 1);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to low\n");
+	gpio_set_value(NETBIRD_GPIO_LATCH, 0);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set final can shield muxing\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_final);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+#define CAN_PORTS	2
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	return (!terminations[0] << 0) | (!terminations[1] << 1);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 3) {
+		debug("Too few arguments for dualcan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+struct shield_t can_shield = {
+	"dualcan", set_shieldmode
+};
+
+void can_shield_init(void)
+{
+	shield_register(&can_shield);
+}
+

board/nm/netbird_v2/shield_can.h

@@ -0,0 +1,9 @@
+#ifndef SHIELD_CAN_H
+#define SHIELD_CAN_H
+
+int shield_can_init(void);
+int shield_can_setmode(int mode);
+
+void can_shield_init(void);
+
+#endif // SHIELD_CAN_H

board/nm/netbird_v2/shield_comio.c

@@ -0,0 +1,251 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LOAD GPIO_TO_PIN(1, 9)
+#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 11)
+#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10)
+
+
+static int shield_slot_initialized = 0;
+
+
+/* V2OK */
+static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux shield_gpio_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Extension slot init\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LOAD, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug ("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type comio\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Enable gpio pull-ups\n");
+	configure_module_pin_mux(shield_gpio_netbird_pin_mux);
+
+	debug("Set load to low\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LOAD, 0);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set load to high\n");
+	gpio_set_value(NETBIRD_GPIO_LOAD, 1);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Disable pullups on shield gpios\n");
+	configure_module_pin_mux(shield_gpio_safe_netbird_pin_mux);
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set gpio load as input again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_LOAD);
+	if (ret < 0) {
+		puts("Can not configure shield slot load as input");
+		return -1;
+	}
+
+	return 0;
+}
+
+enum mode_nr {
+	RS232,
+	RS485,
+	UNKNOWN
+};
+
+struct mode {
+	enum mode_nr nr;
+	const char* name;
+	int argc;
+};
+
+struct mode modes[] = {
+	{RS232, "rs232", 0},
+	{RS485, "rs485", 2}
+};
+
+static const struct mode *get_mode(const char *mode)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		if (strcmp(modes[i].name, mode) == 0) {
+			return &modes[i];
+		}
+	}
+	return NULL;
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int termination = 0;
+	int rs232 = 0;
+	const struct mode *selected_mode;
+
+	assert(argc >= 2);
+
+	if (strcmp ("mode", argv[0])) {
+		debug("Invalid arguments (see help)\n");
+		return -1;
+	}
+
+	selected_mode = get_mode(argv[1]);
+	if (selected_mode == NULL) {
+		debug("Mode %s not supported\n", argv[1]);
+		return -1;
+	}
+
+	debug ("Mode %s, index %d, argc %d\n", selected_mode->name,
+			selected_mode->nr, selected_mode->argc);
+
+	if (selected_mode->argc != argc - 2) {
+		debug("Invalid argument count for mode %s (should %d is %d)\n",
+				argv[1],  selected_mode->argc, argc - 2);
+		return -1;
+	}
+
+	if (selected_mode->nr == RS485) {
+		if (strcmp("termination", argv[2])) {
+			debug("Invalid arguments, do not configure termination\n");
+			return -1;
+		}
+
+		termination = get_termination(argv[3]);
+		if (termination < 0) {
+			debug("Invalid termination %s\n", argv[3]);
+			return -1;
+		}
+	}
+	else {
+		rs232 = 1;
+	}
+
+	/* Termination is inverse */
+	return (rs232 << 0) | ((!termination) << 1);
+}
+
+int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc < 2) {
+		debug("Too few arguments for comio\n");
+		return -1;
+	}
+
+	/* -1 will make configure_shieldmode to faile and is okay therefore */
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+struct shield_t comio_shield = {
+	"comio", set_shieldmode
+};
+
+void comio_shield_init(void)
+{
+	shield_register(&comio_shield);
+}
+

board/nm/netbird_v2/shield_comio.h

@@ -0,0 +1,6 @@
+#ifndef SHIELD_COMIO_H
+#define SHIELD_COMIO_H
+
+void comio_shield_init(void);
+
+#endif // SHIELD_COMIO_H

board/nm/netbird_v2/shield_gnsscan.c

@@ -0,0 +1,143 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_EN_CAN_TERM_N GPIO_TO_PIN(0, 7)
+
+
+static int shield_slot_initialized = 0;
+
+static struct module_pin_mux gnsscan_shield_netbird_pin_mux_final[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E16) UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},	/* CAN1 tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},	/* CAN1 rx */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* EN_CAN1_TERM_N */
+	{-1},
+};
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_EN_CAN_TERM_N, "shield-can-term-n");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 1) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type gnsscan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Set final gnsscan shield muxing\n");
+	configure_module_pin_mux(gnsscan_shield_netbird_pin_mux_final);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set termination on/off\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_EN_CAN_TERM_N, mode);
+	if (ret < 0) {
+		puts("Can not set shield-can-term as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+#define CAN_PORTS	1
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	return (!terminations[0] << 0);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 2) {
+		debug("Too few arguments for gnsscan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+struct shield_t gnsscan_shield = {
+	"gnsscan", set_shieldmode
+};
+
+void gnsscan_shield_init(void)
+{
+	shield_register(&gnsscan_shield);
+}
+

board/nm/netbird_v2/shield_gnsscan.h

@@ -0,0 +1,9 @@
+#ifndef SHIELD_GNSSCAN_H
+#define SHIELD_GNSSCAN_H
+
+int shield_gnsscan_init(void);
+int shield_gnscan_setmode(int mode);
+
+void gnsscan_shield_init(void);
+
+#endif // SHIELD_CAN_H

board/nm/netbird_v2/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/netbird_v2/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

cmd/boot.c

@@ -69,3 +69,14 @@ U_BOOT_CMD(
 	""
 );
 #endif
+
+#ifdef CONFIG_CMD_NB_TEST
+
+extern int do_hwreset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+U_BOOT_CMD(
+	hwreset, 1, 0,	do_hwreset,
+	"Perform HARD RESET of the CPU",
+	""
+);
+#endif /* CONFIG_CMD_NB_TEST */

cmd/fdt.c

@@ -58,7 +58,7 @@ static int fdt_value_setenv(const void *nodep, int len, const char *var)
 	else if (len == 4) {
 		char buf[11];
 
-		sprintf(buf, "0x%08X", *(uint32_t *)nodep);
+		sprintf(buf, "0x%08X", fdt32_to_cpu(*(fdt32_t *)nodep));
 		setenv(var, buf);
 	} else if (len%4 == 0 && len <= 20) {
 		/* Needed to print things like sha1 hashes. */
@@ -740,7 +740,7 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len)
 
 			cp = newp;
 			tmp = simple_strtoul(cp, &newp, 0);
-			*(__be32 *)data = __cpu_to_be32(tmp);
+			*(fdt32_t *)data = cpu_to_fdt32(tmp);
 			data  += 4;
 			*len += 4;
 

common/main.c

@@ -13,6 +13,9 @@
 #include <console.h>
 #include <version.h>
 
+#include <fs.h>
+#include <u-boot/md5.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -20,6 +23,83 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 __weak void show_boot_progress(int val) {}
 
+
+#ifdef CONFIG_NM_LOGIN
+
+/****************************************************************************
+ *  check if ubootpwd exists in data partition and perform a login,
+ *  otherwise continue booting
+ */
+int login (void)
+{
+    #define PASS_LEN 256
+	char stored[16];
+	char buf[PASS_LEN], entered[16];
+	int res, i, tries;
+	loff_t actread;
+
+	puts("\nautoboot has been stopped, press 'e' to enter: ");
+
+	for (i=0; i<=4096; i++) {
+		buf[0] = getc();
+		if (buf[0] == 'e' || buf[0] == '\n') {
+			puts("e");
+			break;
+		}
+		if (i == 4096) return 0;
+	}
+	puts("\n");
+
+	memset(stored, 0x0, sizeof(stored));
+
+    if (fs_set_blk_dev("mmc", "1:3", FS_TYPE_EXT) != 0) {
+        puts("Error, can not set blk devicet");
+        return 1;
+    }
+
+    res = fs_read("/root/boot/bootpass", (ulong)stored, 0, sizeof(stored), &actread);
+	if ((res!=0) || (actread != sizeof(stored))) {
+		/* no file or md5 hash found */
+		puts("Login succeeded\n\n");
+		return 1;
+	}
+
+	for (tries = 1; ; tries++) {
+		puts("\nEnter password: ");
+
+		buf[0] = 0;
+		for (i=0; i<PASS_LEN; i++) {
+			buf[i] = getc();
+			if (buf[i] == '\r' || buf[i] == '\n') {
+				buf[i] = 0;
+				break;
+			}
+		}
+		buf[PASS_LEN-1] = 0;
+
+		if (strlen(buf) > 0) {
+			puts("\n");
+			md5((unsigned char*) buf, strlen(buf), (unsigned char *)entered);
+			if (memcmp(stored, entered, 16) == 0) {
+				break;
+			} else {
+				puts("Login incorrect\n");
+				if (tries == 3) {
+					return 0;
+				}
+			}
+		}
+	}
+
+	/* succeeded */
+	puts("Login succeeded\n\n");
+	return 1;
+}
+
+#endif /* CONIFG_NM_LOGIN */
+
+/****************************************************************************/
+
 static void run_preboot_environment_command(void)
 {
 #ifdef CONFIG_PREBOOT
@@ -65,6 +145,13 @@ void main_loop(void)
 
 	autoboot_command(s);
 
+#ifdef CONFIG_NM_LOGIN
+	if (!login()) {
+		puts ("Login failed, resetting...\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+#endif
+
 	cli_loop();
 	panic("No CLI available");
 }

common/spl/spl.c

@@ -18,6 +18,7 @@
 #include <malloc.h>
 #include <dm/root.h>
 #include <linux/compiler.h>
+#include <spl_version_autogenerated.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -453,7 +454,8 @@ void preloader_console_init(void)
 
 	gd->have_console = 1;
 
-	puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
+	puts("\n" SPL_VERSION "\n");
+	puts("U-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
 			U_BOOT_TIME ")\n");
 #ifdef CONFIG_SPL_DISPLAY_PRINT
 	spl_display_print();

common/spl/spl_mmc.c

@@ -24,11 +24,18 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 	u32 image_size_sectors;
 	unsigned long count;
 	int ret;
+	int nm_additional_header_bytes;
+	int nm_additional_trailer_bytes;
 
 	ret = spl_parse_image_header(header);
 	if (ret)
 		return ret;
 
+	nm_additional_header_bytes = sizeof(struct nm_header) - sizeof(struct image_header);
+	nm_additional_trailer_bytes = sizeof(__be32);
+	spl_image.load_addr -= nm_additional_header_bytes;
+	spl_image.size += nm_additional_header_bytes + nm_additional_trailer_bytes;
+
 	/* convert size to sectors - round up */
 	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
 			     mmc->read_bl_len;
@@ -54,21 +61,32 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
 
 static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 {
+	const unsigned int START_MAGIC = 0x424c5354;
+	const unsigned int END_MAGIC   = 0x424c454e;
+
 	unsigned long count;
+	struct nm_header *nm_header;
 	struct image_header *header;
 	int ret = 0;
+	__be32* end_tag_position;
 
-	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
-					 sizeof(struct image_header));
+	nm_header = (struct nm_header *)(CONFIG_SYS_TEXT_BASE -
+					 sizeof(struct nm_header));
 
 	/* read image header to find the image size & load address */
-	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, nm_header);
 	debug("hdr read sector %lx, count=%lu\n", sector, count);
 	if (count == 0) {
 		ret = -EIO;
 		goto end;
 	}
 
+	if (be32_to_cpu(nm_header->nm_start_tag) != START_MAGIC) return -1;
+	if (be32_to_cpu(nm_header->nm_length)>10000000) return -1;
+	end_tag_position = (__be32*)(((void*)nm_header) + sizeof(struct nm_header) - sizeof(struct image_header) + (be32_to_cpu(nm_header->nm_length)));
+
+	header = &(nm_header->header);
+
 	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
@@ -84,6 +102,8 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 		ret = mmc_load_legacy(mmc, sector, header);
 	}
 
+	if (be32_to_cpu(*end_tag_position) != END_MAGIC) return -1;
+
 end:
 	if (ret) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -92,6 +112,8 @@ end:
 		return -1;
 	}
 
+	printf("Found valid u-boot image at sector %ld\n", sector);
+
 	return 0;
 }
 
@@ -324,6 +346,9 @@ int spl_mmc_load_image(u32 boot_device)
 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
 		err = mmc_load_image_raw_sector(mmc,
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+		if (err)
+			err = mmc_load_image_raw_sector(mmc,
+				CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_ALTERNATE);
 		if (!err)
 			return err;
 #endif

common/xyzModem.c

@@ -60,9 +60,9 @@ static struct
 #endif
 } xyz;
 
-#define xyzModem_CHAR_TIMEOUT            2000	/* 2 seconds */
-#define xyzModem_MAX_RETRIES             20
-#define xyzModem_MAX_RETRIES_WITH_CRC    10
+#define xyzModem_CHAR_TIMEOUT            200	/* 0.2 seconds */
+#define xyzModem_MAX_RETRIES             200
+#define xyzModem_MAX_RETRIES_WITH_CRC    100
 #define xyzModem_CAN_COUNT                3	/* Wait for 3 CAN before quitting */
 
 
@@ -379,7 +379,7 @@ xyzModem_get_hdr (void)
 	  /* Data stream timed out */
 	  xyzModem_flush ();	/* Toss any current input */
 	  ZM_DEBUG (zm_dump (__LINE__));
-	  CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+	  /*CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);*/
 	  return xyzModem_timeout;
 	}
     }
@@ -563,7 +563,7 @@ xyzModem_stream_open (connection_info_t * info, int *err)
 	{
 	  if (--crc_retries <= 0)
 	    xyz.crc_mode = false;
-	  CYGACC_CALL_IF_DELAY_US (5 * 100000);	/* Extra delay for startup */
+	  /*CYGACC_CALL_IF_DELAY_US (5 * 100000);*/	/* Extra delay for startup */
 	  CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
 	  xyz.total_retries++;
 	  ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));

configs/am335x_nbhw16_defconfig

@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NETBIRD=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y

configs/am335x_nbhw16_v2_defconfig

@@ -0,0 +1,631 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# U-Boot 2016.05 Configuration
+#
+CONFIG_CREATE_ARCH_SYMLINK=y
+# CONFIG_ARC is not set
+CONFIG_ARM=y
+# CONFIG_AVR32 is not set
+# CONFIG_BLACKFIN is not set
+# CONFIG_M68K is not set
+# CONFIG_MICROBLAZE is not set
+# CONFIG_MIPS is not set
+# CONFIG_NDS32 is not set
+# CONFIG_NIOS2 is not set
+# CONFIG_OPENRISC is not set
+# CONFIG_PPC is not set
+# CONFIG_SANDBOX is not set
+# CONFIG_SH is not set
+# CONFIG_SPARC is not set
+# CONFIG_X86 is not set
+CONFIG_SYS_ARCH="arm"
+CONFIG_SYS_CPU="armv7"
+CONFIG_SYS_SOC="am33xx"
+CONFIG_SYS_VENDOR="nm"
+CONFIG_SYS_BOARD="netbird_v2"
+CONFIG_SYS_CONFIG_NAME="am335x_netbird_v2"
+
+#
+# ARM architecture
+#
+CONFIG_HAS_VBAR=y
+CONFIG_HAS_THUMB2=y
+CONFIG_CPU_V7=y
+# CONFIG_SEMIHOSTING is not set
+# CONFIG_SYS_L2CACHE_OFF is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_TARGET_EDB93XX is not set
+# CONFIG_TARGET_VCMA9 is not set
+# CONFIG_TARGET_SMDK2410 is not set
+# CONFIG_TARGET_ASPENITE is not set
+# CONFIG_TARGET_GPLUGD is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_KIRKWOOD is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_TARGET_DEVKIT3250 is not set
+# CONFIG_TARGET_WORK_92105 is not set
+# CONFIG_TARGET_MX25PDK is not set
+# CONFIG_TARGET_ZMX25 is not set
+# CONFIG_TARGET_APF27 is not set
+# CONFIG_TARGET_APX4DEVKIT is not set
+# CONFIG_TARGET_XFI3 is not set
+# CONFIG_TARGET_M28EVK is not set
+# CONFIG_TARGET_MX23EVK is not set
+# CONFIG_TARGET_MX28EVK is not set
+# CONFIG_TARGET_MX23_OLINUXINO is not set
+# CONFIG_TARGET_BG0900 is not set
+# CONFIG_TARGET_SANSA_FUZE_PLUS is not set
+# CONFIG_TARGET_SC_SPS_1 is not set
+# CONFIG_ORION5X is not set
+# CONFIG_TARGET_SPEAR300 is not set
+# CONFIG_TARGET_SPEAR310 is not set
+# CONFIG_TARGET_SPEAR320 is not set
+# CONFIG_TARGET_SPEAR600 is not set
+# CONFIG_TARGET_STV0991 is not set
+# CONFIG_TARGET_X600 is not set
+# CONFIG_TARGET_IMX31_PHYCORE is not set
+# CONFIG_TARGET_MX31ADS is not set
+# CONFIG_TARGET_MX31PDK is not set
+# CONFIG_TARGET_WOODBURN is not set
+# CONFIG_TARGET_WOODBURN_SD is not set
+# CONFIG_TARGET_FLEA3 is not set
+# CONFIG_TARGET_MX35PDK is not set
+# CONFIG_ARCH_BCM283X is not set
+# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
+# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
+# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
+# CONFIG_TARGET_KWB is not set
+# CONFIG_TARGET_TSERIES is not set
+# CONFIG_TARGET_CM_T335 is not set
+# CONFIG_TARGET_PEPPER is not set
+# CONFIG_TARGET_AM335X_IGEP0033 is not set
+# CONFIG_TARGET_PCM051 is not set
+# CONFIG_TARGET_DRACO is not set
+# CONFIG_TARGET_THUBAN is not set
+# CONFIG_TARGET_RASTABAN is not set
+# CONFIG_TARGET_PXM2 is not set
+# CONFIG_TARGET_RUT is not set
+# CONFIG_TARGET_PENGWYN is not set
+# CONFIG_TARGET_AM335X_BALTOS is not set
+# CONFIG_TARGET_AM335X_EVM is not set
+# CONFIG_TARGET_AM335X_NETBIRD is not set
+CONFIG_TARGET_AM335X_NETBIRD_V2=y
+# CONFIG_TARGET_AM335X_SL50 is not set
+# CONFIG_TARGET_BAV335X is not set
+# CONFIG_TARGET_TI814X_EVM is not set
+# CONFIG_TARGET_TI816X_EVM is not set
+# CONFIG_TARGET_BCM28155_AP is not set
+# CONFIG_TARGET_BCMCYGNUS is not set
+# CONFIG_TARGET_BCMNSP is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MX7 is not set
+# CONFIG_ARCH_MX6 is not set
+# CONFIG_ARCH_MX5 is not set
+# CONFIG_TARGET_M53EVK is not set
+# CONFIG_TARGET_MX51EVK is not set
+# CONFIG_TARGET_MX53ARD is not set
+# CONFIG_TARGET_MX53EVK is not set
+# CONFIG_TARGET_MX53LOCO is not set
+# CONFIG_TARGET_MX53SMD is not set
+# CONFIG_OMAP34XX is not set
+# CONFIG_OMAP44XX is not set
+# CONFIG_OMAP54XX is not set
+# CONFIG_AM43XX is not set
+# CONFIG_RMOBILE is not set
+# CONFIG_ARCH_SNAPDRAGON is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_TARGET_CM_T43 is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_TARGET_TS4800 is not set
+# CONFIG_TARGET_VF610TWR is not set
+# CONFIG_TARGET_COLIBRI_VF is not set
+# CONFIG_TARGET_PCM052 is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# CONFIG_TEGRA is not set
+# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
+# CONFIG_TARGET_VEXPRESS64_JUNO is not set
+# CONFIG_TARGET_LS2080A_EMU is not set
+# CONFIG_TARGET_LS2080A_SIMU is not set
+# CONFIG_TARGET_LS2080AQDS is not set
+# CONFIG_TARGET_LS2080ARDB is not set
+# CONFIG_TARGET_HIKEY is not set
+# CONFIG_TARGET_LS1021AQDS is not set
+# CONFIG_TARGET_LS1021ATWR is not set
+# CONFIG_TARGET_LS1043AQDS is not set
+# CONFIG_TARGET_LS1043ARDB is not set
+# CONFIG_TARGET_H2200 is not set
+# CONFIG_TARGET_ZIPITZ2 is not set
+# CONFIG_TARGET_COLIBRI_PXA270 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_STM32 is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_TARGET_THUNDERX_88XX is not set
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_MALLOC_F=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+# CONFIG_SPL_DM is not set
+CONFIG_DM_SERIAL=y
+# CONFIG_DM_SPI is not set
+# CONFIG_DM_I2C is not set
+CONFIG_DM_GPIO=y
+# CONFIG_BLK is not set
+# CONFIG_ARMV7_LPAE is not set
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+
+#
+# ARM debug
+#
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DM_KEYBOARD is not set
+# CONFIG_AHCI is not set
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
+
+#
+# Boot images
+#
+CONFIG_SUPPORT_SPL=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+# CONFIG_SPL_SEPARATE_BSS is not set
+CONFIG_FIT=y
+# CONFIG_FIT_VERBOSE is not set
+# CONFIG_FIT_SIGNATURE is not set
+# CONFIG_FIT_BEST_MATCH is not set
+# CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_OF_SYSTEM_SETUP is not set
+# CONFIG_OF_STDOUT_VIA_ALIAS is not set
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+# CONFIG_SPL_LOAD_FIT is not set
+
+#
+# Boot timing
+#
+# CONFIG_BOOTSTAGE is not set
+CONFIG_BOOTSTAGE_USER_COUNT=20
+CONFIG_BOOTSTAGE_STASH_ADDR=0
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+# CONFIG_CONSOLE_RECORD is not set
+
+#
+# Command line interface
+#
+CONFIG_CMDLINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="=> "
+
+#
+# Autoboot options
+#
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+# CONFIG_AUTOBOOT_ENCRYPTION is not set
+CONFIG_AUTOBOOT_DELAY_STR=""
+CONFIG_AUTOBOOT_STOP_STR="s"
+# CONFIG_AUTOBOOT_KEYED_CTRLC is not set
+
+#
+# Commands
+#
+
+#
+# Info commands
+#
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+# CONFIG_CMD_CPU is not set
+# CONFIG_CMD_LICENSE is not set
+
+#
+# Boot commands
+#
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_FDT=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+
+#
+# Environment commands
+#
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EXPORTENV=y
+CONFIG_CMD_IMPORTENV=y
+CONFIG_CMD_EDITENV=y
+# CONFIG_CMD_GREPENV is not set
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_ENV_EXISTS=y
+
+#
+# Memory commands
+#
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_CRC32=y
+# CONFIG_LOOPW is not set
+# CONFIG_CMD_MEMTEST is not set
+# CONFIG_CMD_MX_CYCLIC is not set
+# CONFIG_CMD_MEMINFO is not set
+
+#
+# Device access commands
+#
+CONFIG_CMD_DM=y
+# CONFIG_CMD_DEMO is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ARMFLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
+# CONFIG_CMD_SF is not set
+# CONFIG_CMD_SPI is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_DFU is not set
+# CONFIG_CMD_USB_MASS_STORAGE is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+
+#
+# Shell scripting commands
+#
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+# CONFIG_CMD_SETEXPR is not set
+
+#
+# Network commands
+#
+CONFIG_CMD_NET=y
+# CONFIG_CMD_TFTPPUT is not set
+# CONFIG_CMD_TFTPSRV is not set
+# CONFIG_CMD_RARP is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_CDP is not set
+# CONFIG_CMD_SNTP is not set
+# CONFIG_CMD_DNS is not set
+# CONFIG_CMD_LINK_LOCAL is not set
+
+#
+# Misc commands
+#
+# CONFIG_CMD_CACHE is not set
+# CONFIG_CMD_TIME is not set
+CONFIG_CMD_MISC=y
+# CONFIG_CMD_TIMER is not set
+# CONFIG_CMD_QFW is not set
+
+#
+# Power commands
+#
+
+#
+# Security commands
+#
+
+#
+# Filesystem commands
+#
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SUPPORT_OF_CONTROL=y
+
+#
+# Device Tree Control
+#
+# CONFIG_OF_CONTROL is not set
+CONFIG_NET=y
+# CONFIG_NET_RANDOM_ETHADDR is not set
+# CONFIG_NETCONSOLE is not set
+CONFIG_NET_TFTP_VARS=y
+CONFIG_BOOTP_PXE_CLIENTARCH=0x15
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_DM=y
+CONFIG_DM_WARN=y
+CONFIG_DM_DEVICE_REMOVE=y
+CONFIG_DM_STDIO=y
+CONFIG_DM_SEQ_ALIAS=y
+# CONFIG_SPL_DM_SEQ_ALIAS is not set
+# CONFIG_REGMAP is not set
+# CONFIG_SPL_REGMAP is not set
+# CONFIG_DEVRES is not set
+# CONFIG_ADC is not set
+# CONFIG_ADC_EXYNOS is not set
+# CONFIG_ADC_SANDBOX is not set
+# CONFIG_BLOCK_CACHE is not set
+
+#
+# Clock
+#
+# CONFIG_CLK is not set
+# CONFIG_CPU is not set
+
+#
+# Hardware crypto devices
+#
+# CONFIG_FSL_CAAM is not set
+
+#
+# Demo for driver model
+#
+# CONFIG_DM_DEMO is not set
+
+#
+# DFU support
+#
+CONFIG_DFU_TFTP=y
+
+#
+# DMA Support
+#
+# CONFIG_DMA is not set
+# CONFIG_TI_EDMA3 is not set
+
+#
+# GPIO Support
+#
+# CONFIG_ALTERA_PIO is not set
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_ATMEL_PIO4 is not set
+# CONFIG_INTEL_BROADWELL_GPIO is not set
+# CONFIG_LPC32XX_GPIO is not set
+# CONFIG_MSM_GPIO is not set
+# CONFIG_ROCKCHIP_GPIO is not set
+# CONFIG_VYBRID_GPIO is not set
+# CONFIG_DM_74X164 is not set
+# CONFIG_DM_PCA953X is not set
+
+#
+# I2C support
+#
+# CONFIG_DM_I2C_COMPAT is not set
+# CONFIG_SYS_I2C_DW is not set
+# CONFIG_CROS_EC_KEYB is not set
+
+#
+# LED Support
+#
+# CONFIG_LED is not set
+
+#
+# Mailbox Controller Support
+#
+
+#
+# Memory Controller drivers
+#
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MISC is not set
+# CONFIG_CROS_EC is not set
+# CONFIG_FSL_SEC_MON is not set
+# CONFIG_MXC_OCOTP is not set
+# CONFIG_PWRSEQ is not set
+# CONFIG_PCA9551_LED is not set
+# CONFIG_SYSRESET is not set
+# CONFIG_WINBOND_W83627 is not set
+
+#
+# MMC Host controller Support
+#
+# CONFIG_DM_MMC is not set
+
+#
+# MTD Support
+#
+# CONFIG_MTD is not set
+
+#
+# NAND Device Support
+#
+# CONFIG_NAND_DENALI is not set
+# CONFIG_NAND_VF610_NFC is not set
+# CONFIG_NAND_PXA3XX is not set
+# CONFIG_NAND_ARASAN is not set
+
+#
+# Generic NAND options
+#
+# CONFIG_SPL_NAND_DENALI is not set
+
+#
+# SPI Flash Support
+#
+# CONFIG_SPI_FLASH is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# PCI
+#
+# CONFIG_DM_PCI is not set
+
+#
+# Pin controllers
+#
+# CONFIG_PINCTRL is not set
+
+#
+# Power
+#
+# CONFIG_DM_PMIC is not set
+# CONFIG_DM_REGULATOR is not set
+# CONFIG_DM_PWM is not set
+# CONFIG_RAM is not set
+
+#
+# Remote Processor drivers
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_DM_RTC is not set
+
+#
+# Serial drivers
+#
+CONFIG_REQUIRE_SERIAL_CONSOLE=y
+CONFIG_SERIAL_PRESENT=y
+CONFIG_SPL_SERIAL_PRESENT=y
+# CONFIG_DEBUG_UART is not set
+# CONFIG_DEBUG_UART_SKIP_INIT is not set
+# CONFIG_ALTERA_JTAG_UART is not set
+# CONFIG_ALTERA_UART is not set
+# CONFIG_FSL_LPUART is not set
+CONFIG_SYS_NS16550=y
+# CONFIG_MSM_SERIAL is not set
+
+#
+# Sound support
+#
+# CONFIG_SOUND is not set
+
+#
+# SPI Support
+#
+# CONFIG_FSL_ESPI is not set
+# CONFIG_TI_QSPI is not set
+
+#
+# SPMI support
+#
+# CONFIG_SPMI is not set
+# CONFIG_DM_THERMAL is not set
+
+#
+# Timer Support
+#
+# CONFIG_TIMER is not set
+
+#
+# TPM support
+#
+CONFIG_USB=y
+# CONFIG_DM_USB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_XHCI is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_EHCI is not set
+# CONFIG_USB_DWC3 is not set
+
+#
+# MUSB Controller Driver
+#
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+
+#
+# ULPI drivers
+#
+
+#
+# USB peripherals
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_KEYBOARD is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_DWC2_OTG is not set
+# CONFIG_CI_UDC is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+
+#
+# Graphics support
+#
+# CONFIG_DM_VIDEO is not set
+
+#
+# TrueType Fonts
+#
+# CONFIG_VIDEO_VESA is not set
+# CONFIG_VIDEO_LCD_ANX9804 is not set
+# CONFIG_VIDEO_LCD_SSD2828 is not set
+# CONFIG_VIDEO_MVEBU is not set
+# CONFIG_DISPLAY is not set
+# CONFIG_VIDEO_BRIDGE is not set
+# CONFIG_PHYS_TO_BUS is not set
+
+#
+# File systems
+#
+
+#
+# Library routines
+#
+# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
+CONFIG_HAVE_PRIVATE_LIBGCC=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
+CONFIG_SYS_HZ=1000
+# CONFIG_USE_TINY_PRINTF is not set
+CONFIG_REGEX=y
+# CONFIG_LIB_RAND is not set
+# CONFIG_CMD_DHRYSTONE is not set
+# CONFIG_RSA is not set
+# CONFIG_TPM is not set
+
+#
+# Hashing Support
+#
+# CONFIG_SHA1 is not set
+# CONFIG_SHA256 is not set
+# CONFIG_SHA_HW_ACCEL is not set
+
+#
+# Compression Support
+#
+# CONFIG_LZ4 is not set
+# CONFIG_ERRNO_STR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_SPL_OF_LIBFDT is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_UNIT_TEST is not set

configs/am335x_netbird_v2_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NETBIRD_V2=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+# CONFIG_BOOTP_PXE_CLIENTARCH is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_FPGA is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_PMIC is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set

include/configs/am335x_netbird.h

@@ -0,0 +1,223 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_OMPAP_WATCHDOG
+#undef CONFIG_SPL_WATCHDOG_SUPPORT
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_CMD_NB_TEST
+
+#define CONFIG_NM_LOGIN
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				0 /* 0 means detect from sysboot1 config */
+#define V_SCLK				(V_OSCK)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_image=kernel.bin\0"	\
+	"fdt_image=openwrt-nbhw16.dtb\0"	\
+	"modeboot=sdboot\0" \
+	"fdt_addr=0x82000000\0" \
+	"kernel_addr=0x80000000\0" \
+	"load_addr=0x83000000\0" \
+	"root_part=1\0" /* Default root partition, overwritte in board/mv_ebu/a38x/nbhw14_env.c */ \
+	"add_sd_bootargs=setenv bootargs $bootargs root=/dev/mmcblk1p$root_part rootfstype=ext4 console=ttyO0,115200 rootwait earlyprintk\0" \
+	"add_version_bootargs=setenv bootargs $bootargs\0" \
+	"fdt_skip_update=yes\0" \
+    "ethprime=cpsw\0" \
+	"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
+	"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
+	"sdboot=if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
+			"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
+			"else run sdbringup; fi; " \
+			"run add_sd_bootargs; run add_version_bootargs; " \
+			"bootz $kernel_addr - $fdt_addr; fi\0" \
+	"bootcmd=run sdboot\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; setenv bootargs rdinit=/etc/preinit console=ttyO0,115200 debug; bootz $kernel_addr - $fdt_addr\0"
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_I2C_SPEED                    100000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   50
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET						0x1000  /* The Environment is located at 4k */
+#define CONFIG_ENV_SIZE							0x800	/* The maximum size is 2k */
+#undef  CONFIG_SPL_ENV_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_ONENAND_SUPPORT
+
+
+/* We need to disable SPI to not confuse the eeprom env driver */
+#undef CONFIG_SPI
+#undef CONFIG_SPI_BOOT
+#undef CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/* Fastboot */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+
+#ifdef CONFIG_USB_MUSB_HOST
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_USB_MUSB_GADGET
+/* Removing USB gadget and can be enabled adter adding support usb DM */
+#ifndef CONFIG_DM_ETH
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+#endif /* CONFIG_DM_ETH */
+#endif /* CONFIG_USB_MUSB_GADGET */
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+#define DFU_ALT_INFO_NAND ""
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0xD80000;" \
+	"fdt ram 0x80F80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
+#endif
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
+#define CONFIG_SYS_MEMTEST_START    0x80000000
+#define CONFIG_SYS_MEMTEST_END      0x87900000
+
+/* Enable support for TPS 65218 */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65218
+/* For compatibility reasons (BeagleBone) */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS62362
+
+/* Never enable ISO it is broaken and can lead to a crash */
+#undef CONFIG_ISO_PARTITION
+
+#endif	/* ! __CONFIG_AM335X_EVM_H */

include/configs/am335x_netbird_v2.h

@@ -0,0 +1,246 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_NETBIRD_V2_H
+#define __CONFIG_AM335X_NETBIRD_V2_H
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_OMPAP_WATCHDOG
+#undef CONFIG_SPL_WATCHDOG_SUPPORT
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				0 /* 0 means detect from sysboot1 config */
+#define V_SCLK				(V_OSCK)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT	    200
+#undef CONFIG_NET_RETRY_COUNT
+#define CONFIG_NET_RETRY_COUNT	5
+#define CONFIG_BOOTP_MAY_FAIL
+
+#ifndef CONFIG_SPL_BUILD
+#define KERNEL_ADDR "0x80000000"
+#define LOAD_ADDR "0x83000000"
+#define FDT_ADDR "0x82000000"
+#define PXE_ADDR "0x82800000"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_image=kernel.bin\0"	\
+	"fdt_image=openwrt-nbhw16-nb800.dtb\0"	\
+	"modeboot=sdboot\0" \
+	"fdt_addr=" FDT_ADDR "\0" \
+	"kernel_addr=" KERNEL_ADDR "\0" \
+	"load_addr=" LOAD_ADDR "\0" \
+	"root_part=1\0" /* Default root partition, overwritte in board file */ \
+	"defaultconsole=ttyS1\0" /* Default output console */ \
+	"add_sd_bootargs=setenv bootargs $bootargs root=/dev/${mmc_dev}p$root_part rootfstype=ext4 console=$defaultconsole,115200 rootwait loglevel=4\0" \
+	"add_version_bootargs=setenv bootargs $bootargs\0" \
+	"fdt_skip_update=yes\0" \
+	"ethprime=cpsw\0" \
+	"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
+	"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
+	"sdboot=if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
+			"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
+			"else run sdbringup; fi; " \
+			"run add_version_bootargs;run shieldcmd;run modifyfdtcmd;run add_sd_bootargs;" \
+			"bootz $kernel_addr - $fdt_addr; fi\0" \
+	"bootcmd=run sdboot\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"pxefile_addr_r=" PXE_ADDR "\0" \
+	"fdt_addr_r=" FDT_ADDR "\0" \
+	"kernel_addr_r=" KERNEL_ADDR "\0" \
+	"ramdisk_addr_r=" LOAD_ADDR "\0" \
+	"bootpretryperiod=1000\0" \
+	"tftptimeout=2000\0" \
+	"tftptimeoutcountmax=5\0" \
+	"bootpretryperiod=2000\0" \
+	"autoload=false\0" \
+	"shieldcmd=\0" \
+	"fdtshieldcmd=\0" \
+	/* For v4.19 kernel $mmc_dev should be "mmcblk1" (read from DT), for v3.18 kernel: "mmcblk0". */ \
+	"modifyfdtcmd=fdt addr $fdt_addr;run fdtshieldcmd;if fdt get value mmc_dev /nm_env nm,mmc-dev;then;else setenv mmc_dev mmcblk0;fi\0" \
+	"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 debug; run shieldcmd; run modifyfdtcmd; bootz $kernel_addr - $fdt_addr\0" \
+	"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
+	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" /* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
+
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_CONS_INDEX		2		/* Use UART1 as standard UART (1 = UART0) */
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_I2C_SPEED                    100000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   50
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET						0x1000  /* The Environment is located at 4k */
+#define CONFIG_ENV_SIZE							0x800	/* The maximum size is 2k */
+#undef  CONFIG_SPL_ENV_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_ONENAND_SUPPORT
+
+
+/* We need to disable SPI to not confuse the eeprom env driver */
+#undef CONFIG_SPI
+#undef CONFIG_SPI_BOOT
+#undef CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+
+/* Fastboot */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+
+#ifdef CONFIG_USB_MUSB_HOST
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_USB_MUSB_GADGET
+/* Removing USB gadget and can be enabled adter adding support usb DM */
+#ifndef CONFIG_DM_ETH
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+#endif /* CONFIG_DM_ETH */
+#endif /* CONFIG_USB_MUSB_GADGET */
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_FUNCTION_DFU
+#define CONFIG_DFU_MMC
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+#define DFU_ALT_INFO_NAND ""
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0xD80000;" \
+	"fdt ram 0x80F80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
+#endif
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
+#define CONFIG_SYS_MEMTEST_START    0x80000000
+#define CONFIG_SYS_MEMTEST_END      0x87900000
+
+/* Enable support for TPS 65218 */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65218
+/* For compatibility reasons (BeagleBone) */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS62362
+
+#define CONFIG_CMD_PXE
+
+/* Never enable ISO it is broaken and can lead to a crash */
+#undef CONFIG_ISO_PARTITION
+
+#endif	/* ! __CONFIG_AM335X_NETBIRD_V2_H */

include/configs/ti_armv7_common.h

@@ -220,6 +220,7 @@
 
 /* RAW SD card / eMMC locations. */
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_ALTERNATE 0x1b00 /* address 0x360000  */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 
 /* FAT sd card locations. */

include/image.h

@@ -286,6 +286,14 @@ typedef struct image_header {
 	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
 } image_header_t;
 
+typedef struct nm_header {
+	__be32		nm_start_tag; /* BLST (0x424c5354) */
+	__be32		nm_version;  /* U-boot version number */
+	__be32		nm_length;  /* U-boot image length */
+	uint8_t		reserved[244];  /* Reserved */
+	struct image_header header;
+} nm_header_t;
+
 typedef struct image_info {
 	ulong		start, end;		/* start/end of blob */
 	ulong		image_start, image_len; /* start of image within blob, len of image */

lib/display_options.c

@@ -12,13 +12,15 @@
 #include <version.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
+#include <version_autogenerated.h>
 
 int display_options (void)
 {
+	printf ("\n\n%s\n", UBOOT_VERSION);
 #if defined(BUILD_TAG)
-	printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG);
+	printf ("%s, Build: %s\n\n", version_string, BUILD_TAG);
 #else
-	printf ("\n\n%s\n\n", version_string);
+	printf ("%s\n\n", version_string);
 #endif
 	return 0;
 }