86 lines
2.0 KiB
C
86 lines
2.0 KiB
C
/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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* Common file for ddr code
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*/
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#ifndef __IMX8M_DDR_H__
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#define __IMX8M_DDR_H__
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/arch/ddr.h>
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/* user data type */
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enum fw_type {
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FW_1D_IMAGE,
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FW_2D_IMAGE,
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};
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struct dram_cfg_param {
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unsigned int reg;
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unsigned int val;
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};
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struct dram_fsp_msg {
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unsigned int drate;
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enum fw_type fw_type;
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struct dram_cfg_param *fsp_cfg;
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unsigned int fsp_cfg_num;
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};
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struct dram_timing_info {
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/* umctl2 config */
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struct dram_cfg_param *ddrc_cfg;
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unsigned int ddrc_cfg_num;
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/* ddrphy config */
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struct dram_cfg_param *ddrphy_cfg;
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unsigned int ddrphy_cfg_num;
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/* ddr fsp train info */
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struct dram_fsp_msg *fsp_msg;
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unsigned int fsp_msg_num;
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/* ddr phy trained CSR */
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struct dram_cfg_param *ddrphy_trained_csr;
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unsigned int ddrphy_trained_csr_num;
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/* ddr phy PIE */
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struct dram_cfg_param *ddrphy_pie;
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unsigned int ddrphy_pie_num;
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/* initialized drate table */
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unsigned int fsp_table[4];
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};
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extern struct dram_timing_info dram_timing;
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void ddr_load_train_firmware(enum fw_type type);
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void ddr_init(struct dram_timing_info *timing_info);
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void ddr_cfg_phy(struct dram_timing_info *timing_info);
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void load_lpddr4_phy_pie(void);
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void ddrphy_trained_csr_save(struct dram_cfg_param *, unsigned int);
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void dram_config_save(struct dram_timing_info *, unsigned long);
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/* utils function for ddr phy training */
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void wait_ddrphy_training_complete(void);
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void ddrphy_init_set_dfi_clk(unsigned int drate);
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void ddrphy_init_read_msg_block(enum fw_type type);
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static inline void reg32_write(unsigned long addr, u32 val)
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{
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writel(val, addr);
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}
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static inline u32 reg32_read(unsigned long addr)
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{
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return readl(addr);
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}
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static inline void reg32setbit(unsigned long addr, u32 bit)
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{
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setbits_le32(addr, (1 << bit));
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}
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#define dwc_ddrphy_apb_wr(addr, data) reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(addr), data)
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#define dwc_ddrphy_apb_rd(addr) reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(addr))
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#endif /* __IMX8M_DDR_H__ */
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