Add pinctrl macros for AM62x SoCs. These macro definitions are similar
to that of previous platforms, but adding new definitions to avoid any
naming confusions in the SoC dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The phy used in the 8 bit instance has been changed to the phy used in 4
bit instance on AM62 SoC. This implies the phy configuration required for
both the instances of mmc are similar. Therefore, add a new compatible
for AM62 SoC using the driver data of am64 4 bit instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Fix below compile warnings
drivers/clk/clk-k3.c:329:10: warning: format â%uâ expects argument of type âunsigned intâ, but argument 3 has type âulongâ {aka âlong unsigned intâ} [-Wformat=]
329 | debug("%s: Using better rate %u that gives diff %d\n",
drivers/clk/clk-k3.c:329:10: warning: format â%dâ expects argument of type âintâ, but argument 4 has type âulongâ {aka âlong unsigned intâ} [-Wformat=]
329 | debug("%s: Using better rate %u that gives diff %d\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
commit 11326f3793 upstream.
The prescaler (PTV) setting must be taken into account even when the
timer input clock frequency has been set.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Initialization and power on operations of links have been moved under the
link device in the Sierra SerDes driver. Also, the UCLASS of
sierra_phy_provider has been changed to UCLASS_MISC.
Therefore, fix the probing of SerDes0 instance accordingly.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
In commit 54539583fb ("phy: cadence: Sierra: Add a UCLASS_PHY device for
links"), a separate udevice of type UCLASS_PHY was created for each link.
Therefore, move the corresponding link operations under the link device.
Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the
phy device.
Fixes: 54539583fb ("phy: cadence: Sierra: Add a UCLASS_PHY device for links")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Tested-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Georgi Vlaev <g-vlaev@ti.com>
Add the command "boot_rprocs" that is required for booting remote
processors in U-Boot.
Fixes: 10b387cfae ("include: configs: j721e_evm: Add support to boot ethfw core in j721e")
Fixes: d08dd5f879 ("configs: j721e_hs_evm_a72_defconfig: Sync up the bootcmd with GP configs")
Reported-by: Jesse Villarreal <jesse.villarreal@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
QSGMII PHY initialization should only be done for J721E EVMs and not for
J721E-SK boards. Therefore, fix the environment variables accordingly.
Also, by default remote processors should not be booted in U-Boot but
rather be left to the users to enable this by setting dorprocboot.
Therefore, remove dorprocboot that is being set by default.
Fixes: 10b387cfae ("include: configs: j721e_evm: Add support to boot ethfw core in j721e")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
If CONFIG_BINMAN is set then don't generate tispl.bin and u-boot.img
files using tools/k3_fit_atf.sh
Fixes: 7650825383 ("k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
For HS devices we need to secure each binary before packing
it into the FIT image. The resulting image names need to have
a "_HS" appended to it.
Also ensure that we use SPL DT blobs for tispl.bin
Signed-off-by: Roger Quadros <rogerq@kernel.org>
We need to add u-boot,dm-spl to these nodes so they are available
in the SPL DTB. This is required for NAND to work at SPL.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
This entry type is used to create a secured binary
for use with K3 High Security (HS) devices.
This allows us to no longer depend on k3_fit_atf.sh for
A53 SPL and u-boot image generation even for HS devices.
We still depend on the availability of an external
tool provided by the TI_SECURE_DEV_PKG environment
variable to secure the binaries.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
tee-os is a more appropriate name for OP-TEE binary.
Fixes: dd0bb6313c ("binman: Add support for TEE BL32")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
R5 image building is not yet implemented using Binman. Don't select
CONFIG_BINMAN for R5 build. This should fix boot on AM64 HS.
Fixes: 7650825383 ("k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Add cdns,phy-mode tag in the OSPI NOR flash device tree node to disable
initial read delay calibration and use the read delay value from the device
tree node, during initialization.
Fixes: f8c841752104 ("arm64: dts: k3-j721s2: Add support for OSPI Flashes")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
As the size of tiboot3.bin has increased, the memory layout of the
bootloaders in eMMC and OSPI have been changed to accommodate this.
Therefore, use the dfu environment variables of combined images instead.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
The current size of tiboot3.bin with GP configs is 548KB and the memory
reserved for it in the OSPI flash is 512KB. This leads to overlap of
tiboot3.bin on tispl.bin region and break in OSPI boot mode.
Therefore, fix this by increasing the memory allocated for tiboot3.bin to
1MB.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
The current size of tiboot3.bin with GP configs is 548KB and the memory
reserved for it in eMMC boot partition is 512KB. This leads to overlap of
tiboot3.bin over tispl.bin region and break in eMMC boot mode.
Therefore, fix this by increasing the memory allocated for tiboot3.bin
to 1MB.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
commit 19f7a34a46 upstream.
Add support for enumerating MMC card in a given mode using mmc rescan and
mmc dev commands. The speed mode is provided as the last argument in these
commands and is indicated using the index from enum bus_mode in
include/mmc.h. A speed mode can be set only if it has already been enabled
in the device tree.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Re-enable the ESM driver and this goes along with the patch to enabling
the MCU ESM error reset in MCU control MMR register, after clearing the
main and mcu ESM events on bootup.
This reverts commit ebc8dca63d.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Enable MCUESM error output in MCU reset control register
CTRLMMR_MCU_RST_CTRL, after the Main and MCU ESM events
are cleared on bootup and configured to route the Main ESM
error output to the MCUESM error output.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The ESM for AM64x HS is currently broken. Revert this patch till the ESM
support is fixed for HS.
This reverts commit ba2e5bd756.
Signed-off-by: Yogesh Siraswar <yogeshs@ti.com>
Configure CTRLMMR_MCU_RST_CTRL register only, when the R5 SPL is built
with CONFIG_ESM_K3 flag is set in the board configuration.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Add support to detect daughtercards (GESI Ethernet card) in-order
to set the MAC address of the main CPSW2G interface.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU
minimum voltage is .6V & maximum voltage is .9V.
Correct the same. While at it fix the comment to reflect VDD_CPU
instead of VDD_MPU.
Data Sheet Link: https://www.ti.com/lit/gpn/dra829v
Signed-off-by: Keerthy <j-keerthy@ti.com>
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSPs, and the various Main R5FSS Cores. In order
to view the code loaded by the U-Boot by remote cores, U-Boot should
configure the memory region with right memory attributes. Right now
U-Boot carves out a memory region which is not sufficient for all
the images to be loaded. So, increase this carve out region.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Add aliases for remote procs and support for early boot of remote
processors from A72 u-boot. The remote proc device nodes and shared
memory allocations for IPC and external memory also match with the
kernel device node definitions.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The J721S2 SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0/1). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MAIN domain R5F cluster/subsystems, the two
R5F cores are added as child nodes to a main cluster/subsystem node.
The clusters are configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The J721S2 SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0/1). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MAIN domain R5F cluster/subsystems, the two
R5F cores are added as child nodes to a main cluster/subsystem node.
The clusters are configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
The J721S2 SoCs have two TMS320C71x DSP Subsystems in the MAIN
voltage domain containing the next-generation C711 CPU core.
This subsystem has a CMMU but is not used currently. The inter-
processor communication between the main A72 cores and the C711
processor is achieved through shared memory and a Mailbox. Add the
DT node for these DSP processor sub-systems in the common
k3-j721s2-main.dtsi file.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain,
and there are no C66x DSP subsystems on these SoCs. The C71x DSP subsystem
is a slighly updated version of the C71x DSP subsystem on J721e. The
C71x DSPs are 64 bit machine with fixed and floating point DSP
operations.
Extend support to the C71x DSPs with J721S2 compatible strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The K3 J721S2 SoCs have three dual-core R5F subsystems, one in MCU
voltage domain and the other two in MAIN voltage domain. These R5F
clusters are similar to the R5F clusters in J7200 SoCs.
Compatible Info is updated to support J721S2 SoCs.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The TI K3 J721S2 SoCs have two TM320C71x DSP susbsystems, and does not
have any TMS320C66x DSP subsystems. The C71x DSP subsystems in J721S2
SoCs are similar to the C71x DSP on J721E with some minor core IP
updates.
Compatible info is updated for intuitively matching to the new J721S2
SoCs.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
The TI K3 J721S2 SoCs have three dual-core Arm R5F clusters/subsystems.
One in MCU voltage domain and the other two in MAIN voltage domain.
These clusters are similar to J7200 R5F clusters. Compatible info is
updated for intuitively matching to the new J721S2 SoCs.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Fix the Product ID used by the USB driver.
Fixes: 33008be54b8d ("configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
am64-sk EVM doesn't support daughtercards so let's restrict
daughtercard probing to am64-gp EVM only.
Gets rid of below message at boot on am64-sk EVM
"Failed to lookup gpio gpio@38_0: -22"
Reported-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
After moving to binman image builds we need to include
the appropriate binman file in the k3-am642-sk-u-boot.dtsi
Fixes: 7650825383 ("k3-am642-evm-u-boot: Use binman to generate u-boot.img and tispl.bin")
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Upstream uses $BL31 for ATF blob and will use $BL32 for OP-TEE OS blob.
Since our Yocto build scripts and most of the developer build scripts
pass $ATF and $TEE, we continue to support those if provided.
Their usage should be deprecated. We can then drop this patch once
migration to $BL31 and $BL32 is done.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Introduce k3-am642-evm-binman.dtsi to provide binman configuration.
Provide a third configuration for AM64 EVM with NAND card.
R5 build is still not converted to use binman so restrict binman.dtsi
to A53 build.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Add an entry for OP-TEE Trusted OS 'BL32' payload.
This is required by platforms using Cortex-A cores with TrustZone
technology.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Suman Anna
Vignesh Raghavendra
Aswath Govindraju
Dario Binacchi
Roger Quadros
Hari Nagalla
Yogesh Siraswar
Kishon Vijay Abraham I
Keerthy