Enable configuration required for NAND support on R5 SPL.
We need CONFIG_SOC_DEVICE_TI_K3 to detect the SoC
and apply SoC specific quirks.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Provide NAND device and NAND driver configuration for AM64x EVM.
We are currently using raw NAND partitions for tispl.bin (A53 SPL)
and u-boot.img (A53 u-boot).
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The current way it is implemented chipid node is overridden
in the k3-am642-sk-u-boot.dtsi, losing compatible and other
properties of the chipid node defined in k3-am64-main.dtsi
We simply need to use a label and add "u-boot,dm-spl" property
in k3-am642-sk-u-boot.dtsi.
Fixes: cf26b081da9d ("arm: dts: am642-sk: Add initial sk dts")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The current way it is implemented chipid node is overridden
in the k3-am642-evm-u-boot.dtsi, losing compatible and other
properties of the chpid node defined in k3-am64-main.dtsi
We simply need to use a label and add "u-boot,dm-spl" property
in k3-am642-evm-u-boot.dtsi.
Fixes: 2c91701ba0 ("arm: dts: k3-am64-evm: Make chip id available before pre-reloc")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Add NAND support for A53 SPL, u-boot and R5 SPL.
For A53 SPL & u-boot we use NAND overlay to add NAND support.
For R5 SPL, we include the NAND support in the board DTS file
(k3-am642-r5-evm.dts) as there is no way to use overlay in
BootROM at the moment.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Since we are using overlay for A53 SPL and A53 u-boot the
SPL must select the NAND overlay from the FIT image if
HSE card is present.
For simplicity sake, we only check if a card is present or not in
the HSE (High Speed Expansion) slot to determine if we need to
use NAND overlay.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Adds driver model support.
We need to be able to self initialize the NAND controller/chip
at probe and so enable CONFIG_SYS_NAND_SELF_INIT.
Doing so requires nand_register() API which is provided by nand.c
and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT.
But nand.c also provides nand_init() so we need to get rid of nand_init()
in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Allocate omap_ecclayout on the heap as we have
limited .bss space on AM64 R5 SPL configuration.
Reduces .bss usage by 2984 bytes.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Support NAND SPL loader. We rely on nand_base driver for
detecting the NAND chip, bad block detection and read page.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Fixes the below build warning on 64-bit platforms.
drivers/mtd/nand/raw/nand_spl_loaders.c:26:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
dst = (void *)((int)dst - page_offset);
Signed-off-by: Roger Quadros <rogerq@kernel.org>
nand_bbt.c is not being built with the nand_base driver during SPL
build. This results in build failures if we try to access any nand_bbt
related functions.
Don't use any nand_bbt functions for SPL build.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The BCH detection hardware can generate ECC bytes for multiple
sectors in one go. Use that feature.
correct() only corrects one sector at a time so we need to call it
repeatedly for each sector.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
GPMC is the parent of NAND controller. It needs to be probed
before NAND can work. Use uclass_get_device_by_driver() to
get and activate the GPMC driver.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Some SoCs have a limitation where GPMC reads cannot be less than
32-bits. Add workaround for such SoCs.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Rename omap_nand_read() to omap_nand_read_buf() to reflect
actual behaviour.
Use FIFO read address instead of raw read address for reads.
The GPMC automatically converts 32-bit/16-bit reads to NAND
device specific reads (8/16 bit). Use the largest possible
read granularity size for more efficient reads.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
In certain cases e.g. readid, only lower 8 I/O bits are used.
So for 16-bit devices we need to ensure that the read_buf function
skips the upper 8 I/O bits when returning data.
Provide a 'force_8bit' flag to the read_buf() hook to allow
for that.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Some platforms (e.g. TI AM64) have a limitation that 8-bit
and 16-bit reads do not behave correctly. We need to force 32-bit
reads on such platforms.
Try to use read_buf() ops as much as possible as platform driver
can take care of the quirk. For other places where we cannot use
read_buf() use the quirk flag to limit to 32-bit read.
There are still 2 places where read_byte/read_word is still in use
- nand_block_bad()
- nand_status_op()
A more proper fix will be to move to exec_op() like interface in
the kernel. But for now that might be an overkill.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The omap_elm driver still uses ELM_BASE macro to know the ELM module's
base address. Define it for am642 platform.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
GPMC_CS_NUM is the same thing so use that instead. This will
allow us to get rid of GPMC_MAX_CS from mem.h
Signed-off-by: Roger Quadros <rogerq@kernel.org>
GPMC is a General Purpose Memory Controller module which is
present on many Texas Instruments SoCs.
Use a simple bus class so we can probe its children.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
The ELM module is used for GPMC NAND accesses for detecting
and correcting errors during reads due to NAND bitflips errors.
4-, 8-, and 16-bit error-correction levels are supported using
the BCH (Bose-ChaudhurI-Hocquenghem) algorithm.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Pointer size cannot be assumed to be 32-bit, so use
use uintptr_t instead of uint32_t.
Fixes the below build warning on 64-bit builds.
drivers/mtd/nand/raw/omap_gpmc.c:439:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
head = ((uint32_t) buf) % 4;
Signed-off-by: Roger Quadros <rogerq@kernel.org>
The GPMC module is present on some K2 and K3 SoCs.
Enable building GPMC NAND driver for K2/K3 platforms.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Feedback from u-boot maintainer was to pass NAND partitions
via device tree. Get rid of them from mtdparts cmdline argument.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high ouput through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Add functionality to enable, set priority to the input events and to
route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main
ESM0 error events to MCU ESM. When these error events are routed to MCU
ESM high output, it can trigger the reset logic to reset the device,
when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
Signed-off-by: Bryan Brattlof <bb@ti.com>
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Roger Quadros
Hari Nagalla
Bryan Brattlof
Aswath Govindraju
Swapnil Jakhade