GPU <-> CPU memory inconsistencies have been found in BXS and J721s2.
Every once in a while, the GPU's view of the physical memory differs
from the CPU's view of the physical memory. In such cases, the data
written by CPU to be read by GPU, is not seen by the GPU. This needs
a fix in the Linux GPU driver.
The temporary workaround for now is:
- Set GPU aType to 3 (bypass MSMC coherency)
- Have L3 cache disabled (default in SDK)
This is a temporary fix that will be removed after the 8.4 release.
The GPU driver will then been rewritten to not access memory with
mismatched attributes. Until then undefined behavior will occur
and the following should be avoided:
* Passing the GPU cached buffers (no EXT_image_dma_buf_import)
* Using L3 cache (do not enable it in board config)
* Reuse memory used by the GPU
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
[afd: Rebased on ti-u-boot-2021.01, fixed build warning, fixed commit message]
Signed-off-by: Andrew Davis <afd@ti.com>
DDR configuration for a Jacinto specific board is generated using the
Jacinto 7 DDRSS RegConfig tool. Latest version of the tool is v0.9.1.
It can be obtained from https://www.ti.com/product/TDA4VM#tech-docs under
Technical Documentation > Application note > Jacinto7 DDRSS Register
Configuration Tool.
Updating to contain the generated config of the latest version of the tool.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
commit 75acccd29c ("soc: ti: k3-navss-ringacc: Initialize base address of ring cfg registers")
while adding support for ETHBOOT in AM62x, retrieved "cfg" register address
from AM62x DMSS's main_pktdma and main_bcdma device tree node.
However for AM64x, the "cfg" register entry was not present for the
main_pktdma and main_bcdma nodes, causing network functionality to break in uboot
Fix it here by adding base addresses for "cfg", "tchan", "rchan", "rflow" in main_pktdma
and "cfg", "tchan", "rchan" for main_bcdma.
Fixes: 75acccd29c ("soc: ti: k3-navss-ringacc: Initialize base address of ring cfg registers")
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
The earlycon UART address was unintentionally modifed to uart8 from uart0
by Commit be0386826c ("configs: am6*_evm/j721e_evm: prevent optargs from getting overwritten")
this change caused boot to break in multiple platforms, only J7AEP is configured
to have the earlycon on uart8.
This commit reverts the earlycon MMIO address for AM62x, AM64x, AM65x
and J721E to original expected value 0x02800000 (main_uart0), this fixes the
broken boot for the above platforms.
Fixes: be0386826c ("configs: am6*_evm/j721e_evm: prevent optargs from getting overwritten")
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
This reverts commit 2ad56641d2.
It causes a build break for at least am65x_hs_evm_r5_defconfig, due to
SPL size exceeding limits. Revert it till we can fix cleanly.
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
CONFIG_IS_ENABLED(CADENCE_QSPI_PHY) would check for
CONFIG_SPL_CADENCE_QSPI_PHY when building SPL. But only
CONFIG_CADENCE_QSPI_PHY is defined and used, so calibration ends up not
happening for SPL. Use IS_ENABLED() instead which does not have this
behaviour.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
The entry for DDRSS_PI_321_DATA was accidentally repeated leading to the
last few PI registers being incorrectly programmed.
Fix this.
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory on AM64x and AM62x. Memset can cut the time
in half and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
inititializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory on am625-sk from 10 seconds down
to 1 second. The bist preload function uses the lpddr4 APIs
in the k3-ddrss, so this is compatible with devices with both
16-bit LPDDR4 and 32-bit LPDDR4 interfaces (e.g J721E).
Note: The inline 1-bit ECC feature of the DDRSS is currently
enabled only for AM64x and AM62x.
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
This patch enables the "ddrss" test command for am64x_evm and
am62x_evm. This is a TI vendor command under cmd/ti directory,
replacing the "ddr" test command used in the Keystone-II boards,
with a K3 version. We have to enable TI_COMMON_CMD_OPTIONS to add
the commands from that directory. This option however implies a
group of additional commands we already have in our configs and
others we don't have and don't need.
Enable TI_COMMON_CMD_OPTIONS and CMD_DDRSS and clear the fallout
to preserve the resulting configurations for am64x_evm_a53 and
am62x_evm_a53.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Introduce a new version of the Keystone-II "ddr" command
for testing the inline ECC support in the DDRSS bridge
available on AM62 and AM64. The ECC hardware support in
K3's DDRSS and the test method differ substantially from
what we support in the K2 variant of the command. The
name of the new command is "ddrss".
The ECC test procedure follows these steps:
1) Flush and disable the data cache.
2) Shrink the protected ECC R0 range.
3) Flip a bit outside the shrunk range.
4) Restore the range to original.
5) Read the modified value (corrected).
6) Re-enable the data cache.
This which will cause the 1-bit ECC error count to increase
while the read will return the corrected value.
The K3 version of the command preserves the syntax for the
"ecc_err" argument.
The "ti,am64-ddrss" memory controller node is available only
in the R5 device tree. We don't have Linux kernel support
for DDRSS (e.g EDAC driver) yet, so the command uses a fixed
address as base. Once a Linux kernel consumer is available
we can fetch the DDRSS base from dts.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
The origin of this patch is the breaking of am335x-hs boot
due to commit e41651fffd ("dm: Support parent devices with of-platdata")
HS boards have less SRAM for SPL and so this commit increased memory usage beyond am335x limit.
This commit added 10 driver binding pass and am335x boot only if one pass is done.
SPL try to do more than one pass due to eth_cpsw failing.
Since HS SPL does not need network (and NET is already disabled in config),
the easiest fix is to "remove" eth_cpsw from SPL by testing if NET is enabled.
commit 2f51f946e3 upstream
Signed-off-by: Corentin LABBE <clabbe@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Andrew Davis <afd@ti.com>
Due to supply chain issues, we are starting to see a mixture of eeprom
usage including the smaller 1 byte addressing eeproms such as 24c04
used for eeproms.
These eeproms dont respond well to 2 byte addressing and fail the read
operation. We do have a check to ensure that we are reading the
alternate addressing size, however the previous failure prevents us from
checking any more.
Rectify the same by falling through and depend on header data comparison
to ensure that we have valid data.
Signed-off-by: Nishanth Menon <nm@ti.com>
The eeprom data area is much bigger than the data we intend to store,
however, with bad programming, we might end up reading bad records over
and over till we run out of eeprom space. instead just exit when 10
consecutive records are read.
Signed-off-by: Nishanth Menon <nm@ti.com>
Upstream commit 69076dff22
This adds support for specifying FDT overlays in an extlinux/pxelinux
configuration file.
Without this, there is no simple way to apply overlays when the kernel
and fdt is loaded by the pxe command.
This change adds the 'fdtoverlays' keyword for a label, supporting multiple
overlay files to be applied on top of the fdt specified in the 'fdt' or
'devicetree' keyword.
Example:
label linux
kernel /Image
fdt /soc-board.dtb
fdtoverlays /soc-board-function.dtbo
append console=ttyS0,115200 root=/dev/mmcblk0p2 rootwait
This code makes usage of a new variable called fdtoverlay_addr_r used to load
the overlay files without overwritting anything important.
Cc: Jernej Å krabec <jernej.skrabec@siol.net>
Cc: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lists.denx.de/pipermail/u-boot/2019-May/368388.html
[robertcnelson@gmail.com: Backport to TI u-boot]
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Enable HBMC and HyperFlash related configs in R5 SPL, A72 SPL
and A72 U-Boot.
J721E HS Build was broken due to missing HBMC configs.
Fixes: 70f5dad0ea ("board: ti: j721e: enable hyperflash spl fixup for j721e")
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
On j721e, its not possible to use OSPI0 and HBMC simultaneously as they
are muxed within the Flash Subsystem hence disable HBMC by default and
keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash
mux selection instead of OSPI.
Also updated detect_enable_hyperflash to use correct GPIO when checking
hypermux selection state:
* J7200 - hypermux sel connected to WKUP_GPIO0_6
* J721E - hypermux sel connected to WKUP_GPIO0_8
Fixes Commit 70f5dad0ea ("board: ti: j721e: enable hyperflash spl fixup for j721e")
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Fix issue that saved optargs was getting overwritten when 'run args_all' was called.
This was a issue in all K3 based configurations and is resolved by prepending the
original optargs when set with args_all.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Loading of symbol table depends on DT Overlay support in SPL so make
it compile-time dependent.
Without this fix, SPL fails to boot some platforms where this feature
is not enabled (e.g. dra71-evm.)
Fixes: LCPD-27102
Fixes: 7471fdf830 ("tools/fdtgrep: Include __symbols__ table")
Suggested-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
This reverts commit dcbd681188.
Boot from SD card was broken on dra71-evm, and the breakage was
bisected to this commit. Reverting this commit gets dra71-evm
booting again.
Fixes: LCPD-27102
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
If FIT_IMAGE_POST_PROCESS is set but not SPL_FIT_IMAGE_POST_PROCESS
then board_fit_image_post_process() will not be defined and build
will fail. Use CONFIG_IS_ENABLED to check each at the right stage.
This should not make any change in practice as all boards that define
FIT_IMAGE_POST_PROCESS also define SPL_FIT_IMAGE_POST_PROCESS but this
is more correct.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Anand Gadiyar <gadiyar@ti.com>
We can skip the image authentication check at runtime if the device is GP.
This reduces the delta between GP and HS U-Boot builds. End goal is
to re-unify the two build types into one build that can run on all
device types.
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Anand Gadiyar <gadiyar@ti.com>
On HS-FS devices signing boot images is optional. To ease use
we check if we are HS-FS and if no certificate is attached
to the image we skip the authentication step with a warning
that this will fail when the device is set to security enforcing.
Signed-off-by: Andrew Davis <afd@ti.com>
K3 SoCs are available in a number of device types such as
GP, HS-FS, EMU, etc. Like OMAP SoCs we can detect this at runtime
and should print this out as part of the SoC information line.
We add this as part of the common.c file as it will be used
to also modify our security state early in the device boot.
Signed-off-by: Andrew Davis <afd@ti.com>
Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.
Rather than defining a revision string for each SoC, use a default
revision string array for all TI SoCs that continue to follow the
typical 1.0 -> 2.0 revision scheme.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Fix the boot command to use fitImage.
Fixes: 76952048bb ('configs: Add configs for j721s2 High Security EVM')
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
While configuring SerDes, errors could be encountered, in these cases,
return instead of going ahead. This is will help in booting even if
configuration of SerDes fails.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
implement overrides for spl_spi_boot_bus() lookup function
according to bootmode selection, so as to support both QSPI
and OSPI boot using the same build.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Add OSPI1 description and pinmux node in j721s2-r5 dts which
is necessary for enabling QSPI boot support.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
This reverts commit 246ca5eae0.
SPI NOR core has been updated to use DMA safe buffer during
SFDP read thus making the below check to not use DMA unnecessary.
The check also affects the QSPI read performance significantly.
QSPI Read performance with the check:
=> sf probe 1:0
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> time sf read ${loadaddr} 0x0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
time: 17.621 seconds
QSPI Read performance without check:
=> sf probe 1:0
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> time sf read ${loadaddr} 0x0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
time: 4.032 seconds
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
During sfdp header parse and bfpt parse structures in stack are used
to perform spi_nor_read_sfdp() which expects a dma-safe buffer.
This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap
spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is
the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c).
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
This patchset reimplements part of the dropped patchset bd236384ceef
which enables d-cache during SPL execution.
Having the d-cache disabled created a regression that added additional
250 milliseconds to A72 SPL boot time on the J721E platform.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Add CONFIG_NR_DRAM_BANKS from am62x_evm_a53_defconfig as this is
needed to calculate the size of DDR that is available.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Call into k3-ddrss driver to fixup device tree and resize
the available amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup
as done from R5 SPL and apply it to DT passed to A53 U-boot,
which in turn passes this to the OS.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Use the appropriate fdtdec_setup_mem_size_base()
call in dram_init() and fdtdec_setup_bank_size()
in dram_bank_init() to pull these values from DT,
where they are already available, instead of
hardcoding them.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size used in get_effective_memsize().
Normally, the dram_init_banksize() will set the memory bank
configuration, while the total size is reported in ddr_init().
Since we want to switch to lib/fdtdec for parsing the memory
bank configuration, a call to dram_init_banksize() will no
longer work here. This was possible so far as we set
gd->ram_size in the board's dram_init_banksize().
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Some firewalls enabled by ROM are still left on. So some
address space is inaccessible to the bootloader. For example,
in OSPI boot mode we get an exception and the system hangs.
Therefore, disable all the firewalls left on by the ROM.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Add an entry for Rev 2.0 of the AM64x. With this u-boot now reports the
SoC revision correctly on Rev 2.0 chips.
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Fix the dfu environment variable corresponding to flashing eMMC in devices
that use combined boot flow.
Fixes: 3911240533 ("configs: j721e_evm.h: Fix the dfu environment variables for eMMC and OSPI")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Commit 4d5ca00405 added an spl_spi_boot_cs() override but this has
been removed upstream. So drop that override.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Currently the SPI flash to load from is defined through the compile
time config CONFIG_SF_DEFAULT_BUS and CONFIG_SF_DEFAULT_CS, this
prevents the loading of binaries from different SPI flash using the
same build.E.g. supporting QSPI flash boot and OSPI flash boot
on J721E platform is not possible due to this limitation.
This commit adds lookup functions spl_spi_boot_bus()
and spl_spi_boot_cs for identifying the flash device based on the
selected boot device, when not overridden the lookup functions are
weakly defined in common/spl/spl_spi.c.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add j721s2 High Security EVM defconfig.
These configs are same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_BOOTCOMMAND does not have main_cpsw0_qsgmii_phyinit
variable since j721s2 does not have ethernet firmware.
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Stefan Eichenberger
Neha Malcom Francis
Ravi Gunasekaran
Vaishnav Achath
Anand Gadiyar
Pratyush Yadav
Georgi Vlaev
Corentin LABBE
Nishanth Menon
Neil Armstrong
Matt Ranostay
Kevin Hilman
Andrew Davis
Bryan Brattlof
Jayesh Choudhary
Aswath Govindraju