hw21/26: optimize extension module powerup

fixes 69e9c386dd

arch/arm/Kconfig

@@ -374,6 +374,54 @@ config TARGET_AM335X_EVM
 	select DM_GPIO
 	select TI_I2C_BOARD_DETECT
 
+config TARGET_AM335X_NETBIRD
+	bool "Support am335x_netbird"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_NETBIRD_V2
+	bool "Support am335x_netbird_v2"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_NRHW20
+	bool "Support am335x_nrhw20"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_NMHW21
+        bool "Support am335x_nmhw21"
+        select CPU_V7
+        select SUPPORT_SPL
+        select DM
+        select DM_SERIAL
+        select DM_GPIO
+
+config TARGET_AM335X_NRHW24
+	bool "Support am335x_nrhw24"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_HW25
+	bool "Support am335x_hw25"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
 	select CPU_V7
@@ -870,6 +918,12 @@ source "board/hisilicon/hikey/Kconfig"
 source "board/imx31_phycore/Kconfig"
 source "board/isee/igep0033/Kconfig"
 source "board/mpl/vcma9/Kconfig"
+source "board/nm/netbird/Kconfig"
+source "board/nm/netbird_v2/Kconfig"
+source "board/nm/nrhw20/Kconfig"
+source "board/nm/nmhw21/Kconfig"
+source "board/nm/nrhw24/Kconfig"
+source "board/nm/hw25/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"

arch/arm/cpu/armv7/am33xx/clock_am33xx.c

@@ -21,6 +21,8 @@ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC;
 
+struct ctrl_stat *const ctrlstat = (struct ctrl_stat*)CTRL_BASE;
+
 const struct dpll_regs dpll_mpu_regs = {
 	.cm_clkmode_dpll	= CM_WKUP + 0x88,
 	.cm_idlest_dpll		= CM_WKUP + 0x20,
@@ -53,13 +55,13 @@ const struct dpll_regs dpll_ddr_regs = {
 
 struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core_opp100 = {
-		1000, OSC-1, -1, -1, 10, 8, 4};
-const struct dpll_params dpll_mpu = {
-		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-		50, OSC-1, -1, -1, 1, 1, 1};
-const struct dpll_params dpll_per = {
+struct dpll_params dpll_core_opp100 = {
+  1000, OSC-1, -1, -1, 10, 8, 4};
+struct dpll_params dpll_mpu = {
+  MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+struct dpll_params dpll_core = {
+  50, OSC-1, -1, -1, 1, 1, 1};
+struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
 const struct dpll_params *get_dpll_mpu_params(void)
@@ -113,8 +115,25 @@ void setup_clocks_for_console(void)
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
 }
 
+static inline unsigned long get_osclk_dpll(void)
+{
+	return (get_osclk() / 1000000) - 1;
+}
+
+static inline void am33xx_init_osc_clock(void)
+{
+	unsigned long n = get_osclk_dpll();
+	dpll_mpu_opp100.n = n;
+	dpll_core_opp100.n = n;
+	dpll_mpu.n = n;
+	dpll_core.n = n;
+	dpll_per.n = n;
+}
+
 void enable_basic_clocks(void)
 {
+	am33xx_init_osc_clock();
+
 	u32 *const clk_domains[] = {
 		&cmper->l3clkstctrl,
 		&cmper->l4fwclkstctrl,
@@ -151,6 +170,8 @@ void enable_basic_clocks(void)
 		&cmper->usb0clkctrl,
 		&cmper->emiffwclkctrl,
 		&cmper->emifclkctrl,
+		&cmper->i2c2clkctrl,
+		&cmper->spi1clkctrl,
 		0
 	};
 
@@ -159,3 +180,18 @@ void enable_basic_clocks(void)
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
 }
+
+static unsigned long ram_timings[] = {
+	19200000, 24000000, 25000000, 26000000
+};
+
+unsigned long get_osclk(void)
+{
+	if (V_OSCK != 0) {
+		return V_OSCK;
+	}
+	else {
+		unsigned int sysboot1 = (readl(&ctrlstat->statusreg) >> 22) & 3;
+		return ram_timings[sysboot1];
+	}
+}

arch/arm/cpu/armv7/am33xx/sys_info.c

@@ -123,6 +123,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 {
 	int sil_rev;
 
+/* @@nm@@mr@@ Ignore what the fuse says. 
+	We do not want to go higher than 600 MHZ for now. 
+	This should actually not be needed as it should be overwritten
+	in am33xx_spl_board_init anyway. Just to be sure. 
+	-> Remove it, if really not necessary.
+*/
+return MPUPLL_M_600;
+
 	sil_rev = readl(&cdev->deviceid) >> 28;
 
 	if (sil_rev == 1)

arch/arm/cpu/armv7/omap-common/abb.c

@@ -48,7 +48,7 @@ static void abb_setup_timings(u32 setup)
 	 */
 
 	/* calculate SR2_WTCNT_VALUE */
-	sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000);
+	sys_rate = DIV_ROUND_CLOSEST(get_osclk(), 1000000);
 	clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate);
 	sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles);
 

arch/arm/cpu/armv7/omap-common/timer.c

@@ -33,6 +33,16 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 #define TIMER_OVERFLOW_VAL	0xffffffff
 #define TIMER_LOAD_VAL		0
 
+static inline unsigned long get_timer_clock(void)
+{
+	if (V_SCLK != 0) {
+		return TIMER_CLOCK;
+	}
+	else {
+		return get_osclk() / (2 << CONFIG_SYS_PTV);
+	}
+}
+
 int timer_init(void)
 {
 	/* start the counter ticking up, reload value on overflow */
@@ -55,7 +65,7 @@ ulong get_timer(ulong base)
 /* delay x useconds */
 void __udelay(unsigned long usec)
 {
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	long tmo = usec * (get_timer_clock() / 1000) / 1000;
 	unsigned long now, last = readl(&timer_base->tcrr);
 
 	while (tmo > 0) {
@@ -71,13 +81,13 @@ void __udelay(unsigned long usec)
 ulong get_timer_masked(void)
 {
 	/* current tick value */
-	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	ulong now = readl(&timer_base->tcrr) / (get_timer_clock() / CONFIG_SYS_HZ);
 
 	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
 		gd->arch.tbl += (now - gd->arch.lastinc);
 	} else {	/* we have rollover of incrementer */
-		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (get_timer_clock() /
 				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
 	}
 	gd->arch.lastinc = now;

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h

@@ -32,7 +32,8 @@
 #define CM_DLL_READYST		0x4
 
 extern void enable_dmm_clocks(void);
-extern const struct dpll_params dpll_core_opp100;
+extern unsigned long get_osclk(void);
+extern struct dpll_params dpll_core_opp100;
 extern struct dpll_params dpll_mpu_opp100;
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */

arch/arm/include/asm/arch-am33xx/cpu.h

@@ -410,7 +410,7 @@ struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
 	unsigned int resv2[11];
-	unsigned int clkselmacclk;	/* offset 0x34 */ 
+	unsigned int clkselmacclk;	/* offset 0x34 */
 };
 #endif /* CONFIG_AM43XX */
 
@@ -530,10 +530,12 @@ struct ctrl_dev {
 	unsigned int macid1h;		/* offset 0x3c */
 	unsigned int resv4[4];
 	unsigned int miisel;		/* offset 0x50 */
-	unsigned int resv5[7];
+	unsigned int resv5[4];
+	unsigned int pwmssctrl;		/* offset 0x64 */
+	unsigned int resv6[2];
 	unsigned int mreqprio_0;	/* offset 0x70 */
 	unsigned int mreqprio_1;	/* offset 0x74 */
-	unsigned int resv6[97];
+	unsigned int resv7[97];
 	unsigned int efuse_sma;		/* offset 0x1FC */
 };
 

arch/arm/include/asm/arch-am33xx/spl.h

@@ -47,6 +47,7 @@
 #define BOOT_DEVICE_UART	0x41
 #define BOOT_DEVICE_USBETH	0x44
 #define BOOT_DEVICE_CPGMAC	0x46
+#define BOOT_DEVICE_JTAG        0x58
 
 #define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
 #define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2

board/nm/common/bdparser.h

@@ -0,0 +1,584 @@
+#ifndef _BDPARSER_H
+#define _BDPARSER_H
+/******************************************************************************
+ * (c) COPYRIGHT 2009-2011 by NetModule AG, Switzerland.  All rights reserved.
+ *
+ * The program(s) may only be used and/or copied with the written permission
+ * from NetModule AG or in accordance with the terms and conditions stipulated
+ * in the agreement contract under which the program(s) have been supplied.
+ *
+ * PACKAGE : Board descriptor
+ *
+ * ABSTRACT:
+ *  This package implements board descriptor manipulation functions.
+ *
+ * HISTORY:
+ *  Date      Author       Description
+ *  20091106  rb           RFE-FB18392: created
+ *  20100119  rs           Minor cleanup, tags defined
+ *  20100301  rs           Tags redefined
+ *  20100302  sma          RFE-FB18392: created (partition)
+ *  20100322  th           Adaptation WinCE and Win32 (assert)
+ *                         Added get bd info (type and name for standard entries)
+ *                         Adjusted bd tags
+ *                         Added scan entries (init and get next)
+ *                         Added partition info (flags and types)
+ *                         Added uint64 and partition64
+ *                         Changed boolean value true (BD_TRUE to 1)
+ *  20110104  rs           General code cleanup (style guide), added new tags/types
+ *                         Added bufLen parameter for BD_GetInfo()
+ *                         Fixed wrong sizeof type in GetPartition()
+ *                         Changed 64 bit type to "long long" from struct
+ *                         Added BD_VerifySha1Hmac() function
+ *  20200615  rs           Added BD_Hw_Type tag
+ * 
+ *****************************************************************************/
+
+/**
+ * @file
+ * Board descriptor parser.
+ *  Get() functions are implemented for all supported basis data types:
+ *  - 8/16/32 bits unsigned integers
+ *  - void
+ *  - string
+ *  - IPv4 addresses
+ *  - Ethernet MAC addresses
+ */
+
+/**
+
+\mainpage
+
+\section description    Description
+
+This is the generated documentation for the <b>Board Descriptor utilities</b>.
+
+For more details see the Board Descriptor Design Description.
+
+**/
+
+/*--- component configuration ------------------------------------------------*/
+
+/** Select a target or operating system (just one of course) **/
+#undef BD_TARGET_WIN32
+#undef BD_TARGET_WINCE
+#define BD_TARGET_UBOOT
+#undef BD_TARGET_LINUX
+#undef BD_TARGET_VXWORKS
+
+#undef BD_CONF_UNIT_TESTS      /**< define this to include unit test functions */
+
+#undef BD_CONF_WANT_ASSERT     /**< define this to use assert functions */
+
+#undef BD_CONF_HAS_HASH        /**< set to include hash check functions in parser */
+
+
+/** Define external hmac-sha1 function to use */
+#ifdef BD_CONF_HAS_HASH
+  extern int hmac_sha1(const void* key, unsigned int keylen, const void* data, unsigned int dataLen, void* hash);
+
+  #define BD_SHA1_HASH_FUNC(key, keylen, data, dataLen, hash) \
+            hmac_sha1 (key, keylen, data, dataLen, hash)
+#endif
+
+/** Define desired assert function */
+#ifdef BD_CONF_WANT_ASSERT
+  #ifdef BD_TARGET_WINCE
+    #define BD_ASSERT(test)  ASSERT(test)
+  #elif defined(BD_TARGET_WIN32) && !defined(_DEBUG)
+    /* Win32 Release build */
+    #include <stdio.h>
+    #include <stdlib.h>
+    #define BD_ASSERT(test)  { if(!(test)) { printf("BD_ASSERT(%s)\n- file <%s>\n- line <%d>\n", #test, __FILE__, __LINE__ ); exit(1); } }
+  #elif defined(BD_TARGET_LINUX)
+    #include <linux/kernel.h>
+    #define BD_ASSERT(test)  { if(!(test)) { printk(KERN_NOTICE "BD_ASSERT(%s) %s:%d\n", #test, __FILE__, __LINE__ ); } }
+  #else
+    #include <assert.h>
+    #define BD_ASSERT(test)  assert(test)
+  #endif
+#else
+  /* No assertions wanted */
+  #define BD_ASSERT(test)  ((void) 0)
+#endif /* BD_CONF_WANT_ASSERT */
+
+
+
+/*--- defines ----------------------------------------------------------------*/
+
+#define BD_MAX_LENGTH           (4096)    /**< Maximum length of a board descriptor's payload */
+#define BD_MAX_ENTRY_LEN        (512)     /**< Maximum length of a tag value */
+#define BD_HEADER_LENGTH        (8)       /**< Header is 8 bytes long */
+#define BD_MAX_PARTITION_NAME   (16)      /**< Name of partition is at most 16 chars long*/
+
+
+/*--- types ------------------------------------------------------------------*/
+
+/**
+ * Board Descriptor Tags
+ */
+typedef enum _BD_Tags
+{
+  BD_End                =     0,   /**<  "Void"       -> End tag */
+  BD_Serial             =     1,   /**<  "String"     -> Serial number of the equipment */
+  BD_Production_Date    =     2,   /**<  "Date"       -> Production date of the board */
+  BD_Hw_Ver             =     3,   /**<  "UInt8"      -> Hardware version of the equipment (Major HW changes, potentionally SW relevant) */
+  BD_Hw_Rel             =     4,   /**<  "UInt8"      -> Hardware release of the equipment (Minor HW changes, not SW relevant) */
+  BD_Prod_Name          =     5,   /**<  "String"     -> Human readable product name  */
+  BD_Prod_Variant       =     6,   /**<  "UInt16"     -> Product variant */
+  BD_Prod_Compatibility =     7,   /**<  "String"     -> Product compatibility name */
+
+  BD_Eth_Mac            =     8,   /**<  "MAC"        -> MAC address of the ethernet interface */
+  BD_Ip_Addr            =     9,   /**<  "IPV4"       -> IP V4 address (0.0.0.0 = DHCP) */
+  BD_Ip_Netmask         =    10,   /**<  "IPV4"       -> IP V4 address mask */
+  BD_Ip_Gateway         =    11,   /**<  "IPV4"       -> IP V4 address of the default gateway */
+
+  BD_Usb_Device_Id      =    12,   /**<  "UInt16"      -> USB device ID */
+  BD_Usb_Vendor_Id      =    13,   /**<  "UInt16"      -> USB vendor ID */
+
+  BD_Ram_Size           =    14,   /**<  "UInt32"     -> Available RAM size in bytes */
+  BD_Ram_Size64         =    15,   /**<  "UInt64"     -> Available RAM size in bytes */
+  BD_Flash_Size         =    16,   /**<  "UInt32"     -> Available flash size in bytes */
+  BD_Flash_Size64       =    17,   /**<  "UInt64"     -> Available flash size in bytes */
+  BD_Eeeprom_Size       =    18,   /**<  "UInt32"     -> Available EEPROM size in bytes */
+  BD_Nv_Rram_Size       =    19,   /**<  "UInt32"     -> Available EEPROM size in bytes */
+
+  BD_Cpu_Base_Clk       =    20,   /**<  "UInt32"     -> Base clock of the CPU in Hz = external clock input */
+  BD_Cpu_Core_Clk       =    21,   /**<  "UInt32"     -> Core clock of the CPU in Hz */
+  BD_Cpu_Bus_Clk        =    22,   /**<  "UInt32"     -> Bus clock of the CPU in Hz */
+  BD_Ram_Clk            =    23,   /**<  "UInt32"     -> RAM clock in Hz */
+
+  BD_Partition          =    24,   /**<  "Partition"   -> Offset of 1st Uboot partition in the 1st flash device in bytes */
+  BD_Partition64        =    25,   /**<  "Partition64" -> Offset of 1st Uboot partition in the 1st flash device in bytes */
+
+  BD_Lcd_Type           =    26,   /**<  "UInt16"     -> LCD type -> 0 = not present (interpretation can be project specific) */
+  BD_Lcd_Backlight      =    27,   /**<  "UInt8"      -> LCD backlight setting (0 = off; 100=max) */
+  BD_Lcd_Contrast       =    28,   /**<  "UInt8"      -> LCD contrast setting (0 = min; 100=max) */
+  BD_Touch_Type         =    29,   /**<  "UInt16"     -> Touch Screen type --> 0 = not present/defined */
+
+  BD_Manufacturer_Id    =    30,   /**<  "String"     -> Manufacturer id of the produced equipment (i.e. barcode) */
+  BD_Hmac_Sha1_4        =    31,   /**<  "Hash"       -> SHA1 HMAC with 4 byte result */
+  BD_Fpga_Info          =    32,   /**<  "UInt32"     -> FPGA type/location (0xTTPPRRRR TT=FPGA type, PP=Population location, RRRR=Reserved allways 0000) */
+
+  BD_BOM_Patch          =    33,   /**<  "UInt8"      -> Hardware BOM patch of the equipment (BOM changes, same PCB, not SW relevant) */
+  BD_Prod_Variant_Name  =    34,   /**<  "String"     -> Product variant */
+  BD_Hw_Type            =    35,   /*<<  "UInt16"     -> Hardware Type, e.g. 24 for HW24, 26 for HW26 */
+  
+  BD_Ui_Adapter_Type    =  4096,   /**<  "UInt16"     -> IV OG2 UI adapterboard type (0 = not present) */
+  BD_Voltage            =  4098,   /**<  "UInt8"      -> Primary Voltage (1=12-60V, 2=40-160V, 3=24-60V, 4=?, 5=12-24V) */
+  
+  BD_Pd_Module0         =  4100,   /**<  "String"     -> */
+  BD_Pd_Module1         =  4101,
+  BD_Pd_Module2         =  4102,
+  BD_Pd_Module3         =  4103,
+  BD_Pd_Module4         =  4104,
+  BD_Pd_Module5         =  4105,
+  BD_Pd_Phy0            =  4110,   /**<  "String"     -> */
+  BD_Pd_Phy1            =  4111,   /**<  "String"     -> */
+  BD_Pd_DIO             =  4120,   /**<  "String"     -> */
+  BD_Pd_Serial          =  4121,   /**<  "String"     -> */
+  BD_Pd_Sim             =  4122,   /**<  "String"     -> */
+  BD_Pd_Led             =  4123,   /**<  "String"     -> */
+  BD_Pd_UsbHost         =  4124,   /**<  "String"     -> */
+  PD_Dev_Tree           =  4125,   /**<  "String"     -> Devicetree file name */
+  BD_Patch              =  4126,   /**<  "UInt8"      -> Board patch level (after production) */
+  BD_Pd_Phy2            =  4127,   /**<  "String"     -> */
+  PD_SerDes             =  4128,   /**<  "UInt16"     -> SERDES Configuration (e.g. NB1800) */
+  PD_Shield             =  4129,   /**<  "UInt16"     -> Assembled Shield (0=COM/IO, 1=DualCAN), 2=CAN/GNSS, 3=DualCAN Passive */
+
+  /* project specific tags */
+  BD_BootPart           = 32768,   /**<  "UInt8" */
+
+  BD_None_Type          = 65535,   /**<  "Void"       -> None */
+}
+BD_Tags;
+
+/**
+ * Board Descriptor Tag Types
+ */
+typedef enum _BD_Type
+{
+  BD_Type_End         = 0x00000000,
+  BD_Type_Void        = 0x00000001,
+  BD_Type_UInt8       = 0x00000002,
+  BD_Type_UInt16      = 0x00000003,
+  BD_Type_UInt32      = 0x00000004,
+  BD_Type_UInt64      = 0x00000005,
+  BD_Type_String      = 0x00000010,
+  BD_Type_Date        = 0x00000020,
+  BD_Type_MAC         = 0x00000030,
+  BD_Type_IPV4        = 0x00000040,
+  BD_Type_Partition   = 0x00000050,
+  BD_Type_Partition64 = 0x00000051,
+  BD_Type_HMAC        = 0x00000060,
+  BD_Type_None        = 0xFFFFFFFF,
+}
+BD_Type;
+
+
+typedef unsigned int    bd_uint_t;      /**< Generic UInt */
+typedef unsigned int    bd_size_t;      /**< Size type */
+
+typedef unsigned char   bd_uint8_t;     /**< 8 Bit unsigned integer */
+typedef unsigned short  bd_uint16_t;    /**< 16 Bit unsigned integer */
+typedef unsigned int    bd_uint32_t;    /**< 32 Bit unsigned integer */
+
+#if defined(BD_TARGET_WIN32) || defined (BD_TARGET_WINCE)
+  typedef unsigned __int64 bd_uint64_t;   /**< 64 Bit unsigned integer */
+#else
+  typedef unsigned long long bd_uint64_t; /**< 64 Bit unsigned integer */
+#endif
+
+typedef int             bd_bool_t;      /**< Boolean */
+#define BD_FALSE        0               /**< Boolean FALSE */
+#define BD_TRUE         1               /**< Boolean  TRUE */
+
+typedef struct _BD_Info
+{
+  BD_Tags           tag;
+  BD_Type           type;
+  const char*       pName;
+}
+BD_Info;
+
+typedef struct _BD_Entry
+{
+  bd_uint16_t       tag;           /**< Tag of entry */
+  bd_size_t         len;           /**< Length of entry */
+  bd_uint_t         entry;         /**< Number of entry */
+  const bd_uint8_t* pData;         /**< Pointer to descriptor data of entry */
+}
+BD_Entry;
+
+
+/**
+ * Board Descriptor Context
+ *
+ * This structure is passed to all calls of a Board Descriptor function.
+ * It stores the required context information.
+ * The entries are solely used by the Board Descriptor functions.
+ * They must not be accessed by the user.
+ */
+typedef struct _BD_Context
+{
+  bd_bool_t          headerOk;      /**< True if header check passed else false */
+  bd_bool_t          initialized;   /**< True if data imported (and checked) */
+
+  bd_uint_t          size;          /**< Size of descriptor data */
+  bd_uint_t          entries;       /**< Number of entries found */
+
+  bd_uint16_t        checksum;      /**< Payload checksum contained in the header */
+  const bd_uint8_t*  pData;         /**< Pointer to descriptor data (not header) */
+  const bd_uint8_t*  pDataEnd;      /**< Pointer to end of data */
+}
+BD_Context;
+
+
+/*
+ * Partition Flags
+ */
+typedef enum _BD_Partition_Flags
+{
+  BD_Partition_Flags_None           = 0x00,     /**< No special flags */
+  BD_Partition_Flags_Active         = 0x80,     /**< Partition is active */
+}
+BD_Partition_Flags;
+
+/*
+ * Partition Type
+ */
+typedef enum _BD_Partition_Type
+{
+  BD_Partition_Type_Raw             = 0,        /**< Unspecified type */
+  BD_Partition_Type_Raw_BootLoader  = 1,        /**< Linear bootloader image */
+  BD_Partition_Type_Raw_BBT         = 2,        /**< Bad Block Table */
+  BD_Partition_Type_FS_YAFFS2       = 3,        /**< YAFFS2 Partition */
+  BD_Partition_Type_FS_JFFS2        = 4,        /**< JFFS2 Partition */
+  BD_Partition_Type_FS_FAT16        = 5,        /**< FAT16 Partition */
+  BD_Partition_Type_FS_FAT32        = 6,        /**< FAT32 Partition */
+  BD_Partition_Type_FS_EXFAT        = 7,        /**< EXFAT Partition */
+
+  BD_Partition_Type_Max             = 8,        /**< For error checks */
+}
+BD_Partition_Type;
+
+/*
+ * Partition Options (Partition64 element only)
+ */
+typedef enum _BD_Partition_Options
+{
+  BD_Partition_Opts_None            = 0x00,     /***< No special options */
+  BD_Partition_Opts_ReadOnly        = 0x01,     /***< Partition should be mounted read only */
+  BD_Partition_Opts_OS              = 0x02,     /***< Partition contains operating system (OS) */
+}
+BD_Partition_Options;
+
+/**
+ * Board descriptor type to describe filesystem partitions
+ *
+ * The function BD_GetPartition will directly fill such a structure.
+ */
+typedef struct _BD_PartitionEntry
+{
+  BD_Partition_Flags    flags;
+  BD_Partition_Type     type;
+  bd_uint32_t           offset;
+  bd_uint32_t           size;
+  char                  name[BD_MAX_PARTITION_NAME+1];
+}
+BD_PartitionEntry;
+
+/**
+ * Board descriptor type to describe filesystem partitions
+ *
+ * Extended version with 64 bit addresses and options field.
+ * The function BD_GetPartition64 will directly fill such a structure.
+ */
+typedef struct _BD_PartitionEntry64
+{
+  BD_Partition_Flags    flags;
+  BD_Partition_Type     type;
+  BD_Partition_Options  options;
+  bd_uint64_t           offset;
+  bd_uint64_t           size;
+  char                  name[BD_MAX_PARTITION_NAME+1];
+}
+BD_PartitionEntry64;
+
+
+/*--- function prototypes ----------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Checks a BD header's validity and updates the BD context.
+ *
+ * @param[in,out] pCtx      The context of the BD being checked.
+ * @param[in]     pHeader   Pointer to the BD header
+ * @return        True if the header is valid and the context was updated.
+ *                False if the header s not valid.
+ */
+bd_bool_t BD_CheckHeader( BD_Context* pCtx, const void* pHeader );
+
+/**
+ * Imports BD data from a buffer into a BD context.
+ *
+ * @param[in,out] pCtx      The context into which data is imported.
+ * @param[in]     pData     Pointer to the buffer containing the BD entries.
+ * @return        True if BD entries could be succesfuly imported.
+ *                False if there is an error in the buffer data structure.
+ */
+bd_bool_t BD_ImportData( BD_Context* pCtx, const void* pData );
+
+/**
+ * Checks the existence of a tag in the BD
+ *
+ * @param[in,out] pCtx      The context in which the tag is searched.
+ * @param[in]     tag       Tag being checked.
+ * @param[in]     index     Index of the tag (0=first index).
+ * @return        True if the entry exists in the BD else False.
+ */
+bd_bool_t BD_ExistsEntry( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index );
+
+/**
+ * Get type and name of a tag in the BD info table
+ *
+ * @param[in]     tag       Tag reference.
+ * @param[out]    pType     Type of the tag (0 if not used).
+ * @param[out]    pName     Name of the tag (0 if not used).
+ * @param[in]     bufLen    Length of the pName buffer.
+ *                          If required the returned string for pName will be truncated.
+ * @return        True if the tag in the BD info table exists else False.
+ */
+bd_bool_t BD_GetInfo( bd_uint16_t tag, BD_Type* pType, char* pName, bd_size_t bufLen );
+
+/**
+ * Initialize the entry before use BD_GetNextEntry
+ *
+ * @param[out]    pEntry    BD entry to be initalized.
+ * @return        True if the entry was initialized, fasle otherwise.
+ */
+bd_bool_t BD_InitEntry( BD_Entry* pEntry);
+
+/**
+ * Get type and name of a tag in the BD info table
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[out]    pEntry    BD entry (use BD_InitEntry, not 0 for first ).
+ * @return        True if the tag in the BD info table exists else False.
+ */
+bd_bool_t BD_GetNextEntry( const BD_Context* pCtx, BD_Entry* pEntry );
+
+
+/**
+ * Gets a void value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   True if the value could be found else False.
+ * @return        False if something went wrong dring the parsing else True.
+ */
+bd_bool_t BD_GetVoid( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_bool_t* pResult );
+
+/**
+ * Gets an 8 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt8( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint8_t* pResult );
+
+/**
+ * Gets a 16 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt16( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint16_t* pResult );
+
+/**
+ * Gets a 32 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt32( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult );
+
+/**
+ * Gets a 64 bits unsigned integer value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetUInt64( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint64_t* pResult );
+
+/**
+ * Gets a string value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @param[in]     bufLen    Length of the pResult buffer.
+ * @return        True if the value in pResult is valid else False.
+ *
+ * @note @li The returned string in pResult is null-terminated.
+ *       @li If the buffer is too.small to hold the value the returned string is truncated.
+ */
+bd_bool_t BD_GetString( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, char* pResult, bd_size_t bufLen );
+
+/**
+ * Gets a binary large object (blob) value from a BD.
+ *
+ * @param[in]     pCtx      The context from which the value is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read value.
+ * @param[in]     bufLen    Length of the pResult buffer.
+ * @param[out]    pReadLen  The actual number of bytes read.
+ * @return        True if the complete tag value could be read in pResult else False.
+ */
+bd_bool_t BD_GetBlob( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index,
+                      char* pResult, bd_size_t bufLen, bd_size_t* pReadLen );
+
+/**
+ * Gets an IPv4 address from a BD.
+ *
+ * The IP address is returned as a 32 bits unsigned integer with the most
+ * significant byte first. E.g. 192.168.2.1 is stored as 0xC0A80201
+ *
+ * @param[in]     pCtx      The context from which the IP address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read IP address.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetIPv4( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult );
+
+/**
+ * Gets an Ethernet MAC address from a BD.
+ *
+ * @param[in]     pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the read MAC address.
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetMAC( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, bd_uint8_t pResult[6] );
+
+/**
+ * Gets a partition entry from a BD.
+ *
+ * @param[in,out] pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the partition entry
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetPartition( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry* pResult );
+
+/**
+ * Gets a partition64 entry from a BD.
+ *
+ * @param[in,out] pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[out]    pResult   Placeholder for the partition entry
+ * @return        True if the value in pResult is valid else False.
+ */
+bd_bool_t BD_GetPartition64( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry64* pResult );
+
+
+#ifdef BD_CONF_HAS_HASH
+
+/**
+ * Verifies the SHA1-HMAC checksum.
+ *
+ * The checksum is computed with the specified key over the area defined
+ * by the hash tag. The key must match the one used to generate the descriptor.
+ *
+ * @param[in]     pCtx      The context from which the MAC address is read.
+ * @param[in]     tag       Tag Id.
+ * @param[in]     index     Index of the tag (0=first occurance).
+ * @param[in]     pKey      Pointer to key for HMAC initialization.
+ * @param[in]     keyLen    Size of the key.
+ * @return        True if the protected data is unmodified. False in any other case.
+ */
+bd_bool_t BD_VerifySha1Hmac( const BD_Context* pCtx, bd_uint16_t tag, bd_uint_t index, const void* pKey, bd_size_t keyLen );
+
+#endif
+
+
+#ifdef BD_CONF_UNIT_TESTS
+
+/**
+ * Runs unit tests
+ *
+ * If an error occurs an assert is triggered
+ */
+void BD_UnitTest(void);
+
+#endif /* BD_CONF_UNIT_TESTS */
+
+
+#ifdef __cplusplus
+} /*end extern c*/
+#endif
+
+#endif /* _BDPARSER_H */
+

board/nm/common/board_descriptor.c

@@ -0,0 +1,358 @@
+/******************************************************************************
+ * (c) COPYRIGHT 2010-2019 by NetModule AG, Switzerland.
+ *
+ * The program(s) may only be used and/or copied with the written permission
+ * from NetModule AG or in accordance with the terms and conditions stipulated
+ * in the agreement contract under which the program(s) have been supplied.
+ *
+ * PACKAGE : NetModule Common Hardware Abstraction
+ *
+ * ABSTRACT:
+ *  Board descriptor library
+ *
+ * HISTORY:
+ *  Date      Author       Description
+ *  20100421  SMA          created
+ *  20100903  rs           reading carrier board descriptor from EEPROM at 54.
+ *                         code cleanup (tabs/indentation)
+ *  20110211  rs           partition table handling
+ *  20190330  rs           cleanup after years of chaotic development
+ *  20200615  rs           added bd_get_hw_type()
+ *
+ *****************************************************************************/
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#include "board_descriptor.h"	/* own header file */
+
+
+#define MAX_PARTITION_ENTRIES	4
+
+
+static const BD_Context		*bdctx_list;
+static size_t			bdctx_count = 0;
+
+
+static bd_bool_t _get_string(bd_uint16_t tag, bd_uint_t index, char* pResult, bd_size_t bufLen)
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetString(&bdctx_list[i], tag, index, pResult, bufLen)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_mac(bd_uint16_t tag, bd_uint_t index, bd_uint8_t pResult[6])
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetMAC(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint8(bd_uint16_t tag, bd_uint_t index, bd_uint8_t* pResult)
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt8(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint16(bd_uint16_t tag, bd_uint_t index, bd_uint16_t* pResult)
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt16(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_uint32(bd_uint16_t tag, bd_uint_t index, bd_uint32_t* pResult)
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetUInt32(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static bd_bool_t _get_partition64(bd_uint16_t tag, bd_uint_t index, BD_PartitionEntry64 *pResult)
+{
+	int i;
+
+	for (i = 0; i < bdctx_count; i++) {
+		if (BD_GetPartition64(&bdctx_list[i], tag, index, pResult)) {
+			return BD_TRUE;
+		}
+	}
+
+	return BD_FALSE;
+}
+
+static uint8_t _try_partition_read(void)
+{
+	BD_PartitionEntry64 partition;
+	int i;
+	int rc;
+	int partition_count = 0;
+	int boot_partition = 0;
+
+	for (i = 0; i < MAX_PARTITION_ENTRIES; i++)
+	{
+		rc = _get_partition64(BD_Partition64, i, &partition);
+		if (rc) {
+			partition_count++;
+			if (((partition.flags & BD_Partition_Flags_Active) != 0) &&
+			    (i > 0)) {
+				boot_partition = i;
+			}
+		}
+	}
+
+	if (partition_count < 1) {
+		printf("ERROR: Too few partitions defined, taking default 0\n");
+	}
+
+	return boot_partition;
+}
+
+
+void bd_register_context_list(const BD_Context *list, size_t count)
+{
+	bdctx_list = list;
+	bdctx_count = count;
+}
+
+int bd_get_context(BD_Context *bdctx, uint32_t i2caddress, uint32_t offset)
+{
+	bd_bool_t	rc;
+	uint8_t		bdHeader[8];
+	void*		pBdData = NULL;
+
+	/* Read header bytes from beginning of EEPROM */
+	if (i2c_read( i2caddress, offset, 2, bdHeader, BD_HEADER_LENGTH )) {
+		debug("%s() Can't read BD header from EEPROM\n", __func__);
+		goto exit1;
+	}
+
+	/* Check whether this is a valid board descriptor (or empty EEPROM) */
+	rc = BD_CheckHeader( bdctx, bdHeader );
+	if (!rc) {
+		debug("%s() No valid board descriptor found\n", __func__);
+		goto exit1;
+	}
+
+	/* Allocate memory for descriptor data and .. */
+	pBdData = malloc( bdctx->size );
+	if ( pBdData == NULL ) {
+		debug("%s() Can't allocate %d bytes\n", __func__, bdctx->size);
+		goto exit1;
+	}
+
+	/* .. read data from EEPROM */
+	if (i2c_read(i2caddress, offset+BD_HEADER_LENGTH, 2, pBdData, bdctx->size)) {
+		debug("%s() Can't read data from EEPROM\n", __func__);
+		goto exit1;
+	}
+
+	/*
+	 * Import data into board descriptor context
+	 */
+	rc = BD_ImportData( bdctx, pBdData );
+	if (!rc) {
+		debug("%s() Invalid board descriptor data\n", __func__);
+		goto exit1;
+	}
+
+	return 0;
+
+exit1:
+	if (pBdData != NULL) {
+		free(pBdData);
+		pBdData = NULL;
+	}
+
+	return -1;
+}
+
+int bd_get_prodname(char *prodname, size_t len)
+{
+	if ( !_get_string( BD_Prod_Name, 0, prodname, len) ) {
+		debug("%s() Product name not found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_variantname(char *variantname, size_t len)
+{
+	if ( !_get_string( BD_Prod_Variant_Name, 0, variantname, len) ) {
+		debug("%s() Variant name not found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+void bd_get_hw_type(int* type)
+{
+	uint16_t hwtype = 0;
+
+	if ( !_get_uint16( BD_Hw_Type, 0, &hwtype) )
+		debug("%s() no Hw Type found\n", __func__);
+
+	*type = hwtype;
+}
+
+void bd_get_hw_version(int* ver, int* rev)
+{
+	uint8_t hwver = 0;
+	uint8_t hwrev = 0;
+
+	if ( !_get_uint8( BD_Hw_Ver, 0, &hwver) )
+		debug("%s() no Hw Version found\n", __func__);
+
+	if ( !_get_uint8( BD_Hw_Rel, 0, &hwrev) )
+		debug("%s() no Hw Release found\n", __func__);
+
+	*ver = hwver;
+	*rev = hwrev;
+}
+
+void bd_get_hw_patch(int* patch)
+{
+	uint8_t hwpatch = 0;
+
+	if ( !_get_uint8( BD_BOM_Patch, 0, &hwpatch) )
+		debug("%s() no Hw Patch found\n", __func__);
+
+	*patch = hwpatch;
+}
+
+int bd_get_mac(int index, uint8_t *macaddr, size_t len)
+{
+	if ( len != 6 ) {
+		debug("macaddr size must be 6 (is %d)", len);
+		return -1;
+	}
+
+	/* MAC address */
+	if ( !_get_mac( BD_Eth_Mac, index, macaddr) ) {
+		debug("%s() MAC addresss %d not found\n", __func__, index);
+		return -1;
+	}
+
+	return 0;
+}
+
+uint32_t bd_get_fpgainfo(void)
+{
+	uint32_t fpgainfo = 0xFFFFFFFF;
+
+	if ( !_get_uint32( BD_Fpga_Info, 0, &fpgainfo) )
+		debug("%s() no FGPA Info found\n", __func__);
+
+	return fpgainfo;
+}
+
+int bd_get_pd_dio(char *config, size_t len)
+{
+	if ( !_get_string(BD_Pd_DIO, 0, config, len) ) {
+		debug("%s() no DIO info\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_pd_serial(char *config, size_t len)
+{
+	if ( !_get_string(BD_Pd_Serial, 0, config, len) ) {
+		debug("%s() no serial port info\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_pd_module(uint32_t slot, char *config, size_t len)
+{
+	if ( !_get_string(BD_Pd_Module0 + slot, 0, config, len) ) {
+		debug("%s() could not read module configuration on slot %d\n",
+				__func__, slot);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_sim_config(char* simconfig, size_t len)
+{
+	if (!_get_string(BD_Pd_Sim, 0, simconfig, len)) {
+		debug("%s() no valid SIM config found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_devicetree(char* devicetreename, size_t len)
+{
+	if (!_get_string(PD_Dev_Tree, 0, devicetreename, len)) {
+		debug("%s() no valid devicetree name found\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int bd_get_shield(uint32_t shieldnr)
+{
+	bd_uint16_t shield = 0;
+
+	if (!_get_uint16(PD_Shield, shieldnr, &shield) ) {
+		debug("%s() no shield populated\n", __func__);
+		return -1;
+	}
+
+	return shield;
+}
+
+uint8_t bd_get_boot_partition(void)
+{
+	uint8_t boot_part;
+
+	/* If we have a Bootpartition entry take this as boot part */
+	if (_get_uint8( BD_BootPart, 0, &boot_part) ) {
+		if (boot_part >= 0 && boot_part <= 1) {
+			return boot_part;
+		}
+	}
+
+	/* If we don't have a Bootpartition entry, perhaps we have a partition table */
+	return _try_partition_read();
+}

board/nm/common/board_descriptor.h

@@ -0,0 +1,33 @@
+/*
+ * Board descriptor library
+ *
+ * (c) COPYRIGHT 2010-2019 by NetModule AG, Switzerland.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOARD_DESCRIPTOR_H
+#define __BOARD_DESCRIPTOR_H
+
+#include "bdparser.h"		/* BD_Context */
+
+
+void bd_register_context_list(const BD_Context *list, size_t count);
+int bd_get_context(BD_Context *bdctx, uint32_t i2caddress, uint32_t offset);
+
+int bd_get_prodname(char *prodname, size_t len);
+int bd_get_variantname(char *variantname, size_t len);
+void bd_get_hw_type(int* type);
+void bd_get_hw_version(int* ver, int* rev);
+void bd_get_hw_patch(int* patch);
+int bd_get_mac(int index, uint8_t *macaddr, size_t len);
+uint32_t bd_get_fpgainfo(void);
+int bd_get_pd_dio(char *config, size_t len);
+int bd_get_pd_serial(char *config, size_t len);
+int bd_get_pd_module(uint32_t slot, char *config, size_t len);
+int bd_get_sim_config(char* simconfig, size_t len);
+int bd_get_devicetree(char* devicetreename, size_t len);
+int bd_get_shield(uint32_t shieldnr);
+uint8_t bd_get_boot_partition(void);
+
+#endif	/* __BOARD_DESCRIPTOR_H */

board/nm/common/da9063.c

@@ -0,0 +1,139 @@
+/*
+ * da9063.c
+ *
+ * Dialog DA9063 PMIC
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+
+#include "da9063.h"
+
+
+static int da9063_i2c_bus = 0;
+static int bus_claimed = 0;
+
+
+static int switch_i2c_bus(void)
+{
+	int old_bus;
+
+	old_bus = i2c_get_bus_num();
+	if (old_bus != da9063_i2c_bus) {
+		i2c_set_bus_num(da9063_i2c_bus);
+	}
+
+	bus_claimed++;
+
+	return old_bus;
+}
+
+static void revert_i2c_bus(int bus)
+{
+	if (da9063_i2c_bus != bus) {
+		i2c_set_bus_num(bus);
+	}
+
+	bus_claimed--;
+}
+
+
+void da9063_init(int i2c_bus)
+{
+	da9063_i2c_bus = i2c_bus;
+}
+
+int da9063_claim_i2c_bus(void)
+{
+	return switch_i2c_bus();
+}
+
+void da9063_release_i2c_bus(int bus)
+{
+	revert_i2c_bus(bus);
+}
+
+int da9063_get_reg(uint32_t reg, uint8_t* val)
+{
+	int ret;
+	uint8_t temp;
+
+	/* Argument check */
+	if ((reg >= 0x200) || (val==0)) {
+		return -1;
+	}
+
+	/* State check. Has bus been claimed */
+	if (bus_claimed == 0) {
+		return -2;
+	}
+
+	*val = 0;
+	if (reg < 0x100) {
+		ret = i2c_read(CONFIG_PMIC_I2C_ADDR+0, reg & 0xFF, 1, &temp, 1);
+	} else {
+		ret = i2c_read(CONFIG_PMIC_I2C_ADDR+1, reg & 0xFF, 1, &temp, 1);
+	}
+
+	if (ret == 0)
+		*val = temp;
+
+	return ret;
+}
+
+int da9063_set_reg(uint32_t reg, uint8_t val)
+{
+	int ret;
+
+	/* Argument check */
+	if (reg >= 0x200) {
+		return -1;
+	}
+
+	/* State check. Has bus been claimed */
+	if (bus_claimed == 0) {
+		return -2;
+	}
+
+	if (reg < 0x100) {
+		ret = i2c_write(CONFIG_PMIC_I2C_ADDR+0, reg & 0xFF, 1, &val, 1);
+	} else {
+		ret = i2c_write(CONFIG_PMIC_I2C_ADDR+1, reg & 0xFF, 1, &val, 1);
+	}
+
+	if (ret != 0)
+		puts("da9063 write error\n");
+
+	return ret;
+}
+
+void da9063_set_gpio(unsigned bit, int state)
+{
+	int pmic_reg;
+	int ret;
+	uint8_t bitmask;
+	uint8_t reg = 0x00;
+
+	if (bit <= 7) {
+		pmic_reg = PMIC_REG_GPIO_MODE0_7;
+		bitmask = 1U << (bit-0);
+	}
+	else  {
+		pmic_reg = PMIC_REG_GPIO_MODE8_15;
+		bitmask = 1U << (bit-8);
+	}
+
+	ret = da9063_get_reg(pmic_reg, &reg);
+
+	if (ret == 0)  {
+		if (state)	reg |=  bitmask;
+		else		reg &= ~bitmask;
+
+		(void)da9063_set_reg(pmic_reg, reg);
+	}
+}

board/nm/common/da9063.h

@@ -0,0 +1,103 @@
+/*
+ * da9063.c
+ *
+ * Dialog DA9063 PMIC
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef DA9063_H
+#define DA9063_H
+
+
+#define CONFIG_PMIC_I2C_BUS	0
+#define CONFIG_PMIC_I2C_ADDR	0x58	/* Pages 0 and 1, Pages 2 and 3 -> 0x59 */
+
+#define PMIC_REG_STATUS_A		0x01	/* Status of ON_KEY, WAKE, COMP1V2, DVC */
+#define PMIC_REG_STATUS_A_COMP1V2_MASK	0x08
+
+#define PMIC_REG_FAULT_LOG		0x05	/* PMIC fault log register, holding reset reason */
+#define PMIC_FAULT_TWD_ERROR_MASK	0x01	/* Watchdog timeout detected */
+#define PMIC_FAULT_POR_MASK		0x02	/* Startup from No-Power/RTC/Delivery mode */
+
+#define PMIC_REG_EVENT_A		0x06
+#define PMIC_REG_EVENT_ONKEY_MASK	0x01
+#define PMIC_REG_EVENT_RTC_ALARM_MASK	0x02
+#define PMIC_REG_EVENT_RTC_TICK_MASK	0x04
+#define PMIC_REG_EVENT_EVENTS_B_MASK	0x20
+
+#define PMIC_REG_EVENT_B		0x07
+#define PMIC_REG_EVENT_COMP1V2_MASK	0x04
+
+#define PMIC_REG_IRQ_MASK_A	0x0A
+#define PMIC_REG_IRQ_MASK_B	0x0B
+#define PMIC_REG_IRQ_MASK_C	0x0C
+#define PMIC_REG_IRQ_MASK_D	0x0D
+
+#define PMIC_REG_CONTROL_A      0x0E    /* Control register for power states */
+#define PMIC_REG_CONTROL_D	0x11    /* Control register for blink/watchdog */
+#define PMIC_REG_GPIO14_15	0x1C    /* Configuration of GPIO14/15 (mode, wake) */
+#define PMIC_REG_GPIO_MODE0_7	0x1D	/* Control register for GPIOs 0..7 */
+#define PMIC_REG_GPIO_MODE8_15	0x1E	/* Control register for GPIOs 8..15 */
+
+#define PMIC_REG_BCORE1_CONT	0x21	/* Control register of BCORE1 */
+#define PMIC_REG_BCORE2_CONT	0x20	/* Control register of BCORE2 */
+#define PMIC_REG_BPERI_CONT	0x25	/* Control register of BPERI */
+#define PMIC_REG_BIO_CONT	0x24	/* Control register of BIO */
+#define PMIC_REG_BMEM_CONT	0x23	/* Control register of BMEM */
+
+#define PMIC_REG_LDO3_CONT	0x28	/* Control register of LDO3 */
+#define PMIC_REG_LDO6_CONT	0x2B	/* Control register of LDO6 */
+#define PMIC_REG_LDO7_CONT	0x2C	/* Control register of LDO7 */
+#define PMIC_REG_LDO11_CONT	0x30	/* Control register of LDO11 */
+
+#define PMIC_LDOx_EN_MASK	0x01
+#define PMIC_LDOx_CONF_MASK	0x80
+
+#define PMIC_REG_ID_4_3		0x84
+#define PMIC_REG_ID_6_5		0x85
+
+#define PMIC_REG_BUCK_ILIM_A	0x9A
+#define PMIC_REG_BUCK_ILIM_B	0x9B
+#define PMIC_REG_BUCK_ILIM_C	0x9C
+
+#define PMIC_REG_BCORE1_CONF	0x9E	/* Configuration register of BCORE1 */
+#define PMIC_REG_BCORE2_CONF	0x9D	/* Configuration register of BCORE2 */
+#define PMIC_REG_BPERI_CONF	0xA2	/* Configuration register of BPERI */
+#define PMIC_REG_BIO_CONF	0xA0	/* Configuration register of BIO */
+#define PMIC_REG_BMEM_CONF	0xA1	/* Configuration register of BMEM */
+
+#define PMIC_CONF_MODE_MASK	0xC0
+#define PMIC_CONF_MODE_SLEEP	0x40
+#define PMIC_CONF_MODE_SYNC	0x80
+#define PMIC_CONF_MODE_AUTO	0xC0
+
+
+#define PMIC_REG_BBAT_CONT	0xC5	/* Control register for backup battery */
+
+#define PMIC_REG_CONFIG_E	0x10A
+#define PMIC_REG_CONFIG_G	0x10C
+#define PMIC_REG_CONFIG_L	0x111
+
+#define PMIC_REG_TRIM_CLDR	0x120	/* Calendar Trim register, 2's complement, 1.9ppm per bit */
+
+#define PMIC_GP_ID_0		0x121	/* General purpose ID 0 (R/W) */
+#define PMIC_GP_ID_1		0x122	/* General purpose ID 1 (R/W) */
+
+#define PMIC_REG_CONFIG_ID	0x184	/* OTP Config ID <ver.rev> */
+
+
+extern void da9063_init(int i2c_bus);
+
+extern int da9063_claim_i2c_bus(void);
+extern void da9063_release_i2c_bus(int bus);
+
+extern int da9063_get_reg(uint32_t reg, uint8_t* val);
+extern int da9063_set_reg(uint32_t reg, uint8_t val);
+
+extern void da9063_set_gpio(unsigned bit, int state);
+
+
+#endif /* DA9063_H */

board/nm/common/ether_crc.c

@@ -0,0 +1,36 @@
+/*
+ * ether_crc.c
+ *
+ * Ethernet CRC computation
+ *
+ * Copyright (C) 2018-2020 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "ether_crc.h"
+
+
+uint32_t ether_crc(size_t len, uint8_t const *p)
+{
+	uint32_t crc;
+	unsigned i;
+
+	crc = ~0;
+	while (len--) {
+		crc ^= *p++;
+		for (i = 0; i < 8; i++)
+			crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+	}
+
+	/* an reverse the bits, cuz of way they arrive -- last-first */
+	crc = (crc >> 16) | (crc << 16);
+	crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
+	crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
+	crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
+	crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
+	
+	return crc;
+}

board/nm/common/ether_crc.h

@@ -0,0 +1,18 @@
+/*
+ * ether_crc.h
+ *
+ * Ethernet CRC computation
+ *
+ * Copyright (C) 2018-2020 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ETHER_CRC_H
+#define ETHER_CRC_H
+
+
+extern uint32_t ether_crc(size_t len, uint8_t const *p);
+
+
+#endif /* ETHER_CRC_H */

board/nm/hw25/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_HW25
+
+config SYS_BOARD
+        default "hw25"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_hw25"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 1
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/hw25/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o ../common/da9063.o ../common/ether_crc.o fileaccess.o

board/nm/hw25/board.h

@@ -0,0 +1,26 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
+#endif

board/nm/hw25/fileaccess.c

@@ -0,0 +1,40 @@
+#include <common.h>
+#include <fs.h>
+
+#define BLOCK_DEVICE "mmc"
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	/* Read at most file size bytes */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}

board/nm/hw25/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/hw25/mux.c

@@ -0,0 +1,223 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* CPU GPIOs
+	*
+	* (J18) GPIO0_16: RST_PHY~
+	* (U10) GPIO0_22: SEL_RS232/RS485~
+	* (T10) GPIO0_23: EN_RS485_TERM~
+	* (T11) GPIO0_26: IO_OUT1
+	* (U12) GPIO0_27: IO_OUT2
+	*
+	* (T12) GPIO1_12: IO_IN0
+	* (T13) GPIO1_13: IO_IN1
+	* (T14) GPIO1_14: IO_IN2
+	* (T15) GPIO1_15: IO_IN3
+	*
+	* (T13) GPIO2_0: RST_SDCARD~
+	* (L17) GPIO2_18: GSM_PWR_EN
+	* (L16) GPIO2_19: RST_GSM
+	*
+	* (K18) GPIO3_9: WLAN_IRQ
+	* (L18) GPIO3_10: WLAN_EN
+	* (C12) GPIO3_17: SIM_SEL
+	*/
+
+	/* Bank 0 */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)},				/* (U10) gpio0[22] */  /* SEL_RS232/RS485~ */
+	{OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)},				/* (T10) gpio0[23] */  /* EN_RS485_TERM~ */
+	{OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)},				/* (T11) gpio0[26] */  /* IO_OUT1 */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},				/* (U12) gpio0[27] */  /* IO_OUT2 */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_ad12), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (T12) gpio1[12] */  /* IO_IN0 */
+	{OFFSET(gpmc_ad13), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (R12) gpio1[13] */  /* IO_IN1 */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V13) gpio1[14] */  /* IO_IN2 */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (U13) gpio1[15] */  /* IO_IN3 */
+
+	/* TODO: What about all the unused GPMC pins ? */
+
+	/* Bank 2 */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},				/* (T13) gpio2[0] */  /* RST_SDCARD~ */
+	{OFFSET(mii1_rxd3), (MODE(7) | PULLUDDIS)},				/* (L17) gpio2[18] */  /* GSM_PWR_EN */
+	{OFFSET(mii1_rxd2),  (MODE(7) | PULLUDDIS)},				/* (L16) gpio2[19] */  /* RST_GSM */
+
+
+#if 0
+	/* TODO: What is this meant for? */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (R4) gpio2[9] */  /* SYSBOOT_3 */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (T1) gpio2[10] */  /* SYSBOOT_4 */
+
+	/* TODO: Check other unued pins from sysboot block */
+	/* Ensure PU/PD does not work against external signal */
+	/*
+	 * SYSBOOT 0,1,5,12,13 = Low
+	 * SYSBOOT 2 = High
+	 */
+#endif
+
+	/* Bank 3 */
+	{OFFSET(mii1_txclk),  (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (K18) gpio3[9] */  /* WLAN_IRQ */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},				/* (L18) gpio3[10] */  /* WLAN_EN */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (C12) gpio3[17] */  /* SIM_SEL */
+	{-1}
+};
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1}
+};
+
+/* I2C2 System */
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D17) I2C2_SCL */
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D18) I2C2_SDA */
+	{-1},
+};
+
+/* RMII1: Ethernet */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio (rxerr) */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for PHY) */
+	{-1}
+};
+
+/* RMII2: Ethernet */
+static struct module_pin_mux rmii2_pin_mux[] = {
+	/* RMII */
+	{OFFSET(gpmc_a9), MODE(3) | PULLUDDIS | RXACTIVE},			/* (U16) rmii2_crs */
+	{OFFSET(gpmc_wpn), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (U17) gpio (rxerr) */
+	{OFFSET(gpmc_a11), MODE(3) | PULLUDDIS | RXACTIVE},			/* (V17) rmii2_rxd0 */
+	{OFFSET(gpmc_a10), MODE(3) | PULLUDDIS | RXACTIVE},			/* (T16) rmii2_rxd1 */
+	{OFFSET(gpmc_a0), MODE(3) | PULLUDDIS},					/* (R13) rmii2_txen */
+	{OFFSET(gpmc_a5), MODE(3) | PULLUDDIS},					/* (V15) rmii2_txd0 */
+	{OFFSET(gpmc_a4), MODE(3) | PULLUDDIS},					/* (R14) rmii2_txd1 */
+	{OFFSET(mii1_col), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H16) rmii2_refclk */
+	{-1},
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1}
+};
+
+/* UART0: User (Debug/Console) */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* UART5: RS232/RS485 */
+/* CTS is unused - set to GPIO mode */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(7) | PULLUDEN | PULLDOWN_EN)},			/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1}
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1}
+};
+
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(rmii2_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c2_pin_mux);
+
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+

board/nm/hw25/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+                board/nm/hw25/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/netbird/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NETBIRD
+
+config SYS_BOARD
+        default "netbird"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_netbird"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 1
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/netbird/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o

board/nm/netbird/board.c

@@ -0,0 +1,550 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <serial.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65218.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "../common/bdparser.h"
+#include "../common/board_descriptor.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+
+#define NETBIRD_GPIO_RST_PHY_N	GPIO_TO_PIN(0, 16)
+#define NETBIRD_GPIO_PWR_GSM	GPIO_TO_PIN(1, 22)
+#define NETBIRD_GPIO_RST_GSM	GPIO_TO_PIN(1, 24)
+#define NETBIRD_GPIO_WLAN_EN	GPIO_TO_PIN(3, 10)
+#define NETBIRD_GPIO_BT_EN		GPIO_TO_PIN(3, 4)
+#define NETBIRD_GPIO_EN_GPS_ANT	GPIO_TO_PIN(2, 24)
+#define NETBIRD_GPIO_LED_A		GPIO_TO_PIN(1, 14)
+#define NETBIRD_GPIO_LED_B		GPIO_TO_PIN(1, 15)
+#define NETBIRD_GPIO_RESET_BUTTON	GPIO_TO_PIN(1, 13)
+
+#define DDR3_CLOCK_FREQUENCY (400)
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+
+#define BD_EEPROM_ADDR			(0x50)	/* CPU BD EEPROM (8kByte) is at 50 (A0) */
+#define BD_ADDRESS				(0x0000)  /* Board descriptor at beginning of EEPROM */
+#define PD_ADDRESS				(0x0200)  /* Product descriptor */
+#define PARTITION_ADDRESS		(0x0600)  /* Partition Table */
+
+static BD_Context   bdctx[3];		/* The descriptor context */
+
+static int _bd_init(void)
+{
+	if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
+		printf("%s() no valid bd found\n", __func__);
+		return -1;
+	}
+
+	if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
+		printf("%s() no valid pd found (legacy support)\n", __func__);
+	}
+
+	if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
+		printf("%s() no valid partition table found\n", __func__);
+	}
+
+	bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
+    return 0;
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static inline int __maybe_unused read_eeprom(void)
+{
+    return _bd_init();
+}
+
+struct serial_device *default_serial_console(void)
+{
+	return &eserial1_device;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_netbird_data = {
+	/* Ratios were optimized by DDR3 training software from TI */
+	.datardsratio0 = 0x37,
+	.datawdsratio0 = 0x42,
+	.datafwsratio0 = 0x98,
+	.datawrsratio0 = 0x7a,
+};
+
+static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_netbird_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = 0x61A,	/* 32ms > 85°C */
+	.sdram_tim1 = 0x0AAAE51B,
+	.sdram_tim2 = 0x246B7FDA,
+	.sdram_tim3 = 0x50FFE67F,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_relocate_spec();
+	if (getenv_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+struct dpll_params dpll_ddr_nbhw16= {
+		DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CPU speed to 600 MHZ */
+	dpll_mpu_opp100.m = MPUPLL_M_600;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Clear th PFM Flag on DCDC4 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_DCDC4, 0x00, 0x80)) {
+		puts ("tps65218_reg_write failure\n");
+	};
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	dpll_ddr_nbhw16.n = (get_osclk() / 1000000) - 1;
+	return &dpll_ddr_nbhw16;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+
+const struct ctrl_ioregs ioregs_netbird = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+	config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
+		   &ddr3_netbird_data,
+		   &ddr3_netbird_cmd_ctrl_data,
+		   &ddr3_netbird_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+static void request_and_set_gpio(int gpio, char *name, int value)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, value);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLEAR_GPIO(N)	request_and_set_gpio(N, #N, 0);
+
+
+int check_reset_button(void)
+{
+	int counter = 0;
+	int ret;
+
+	ret = gpio_request(NETBIRD_GPIO_RESET_BUTTON, "reset button");
+	if (ret < 0) {
+		printf("Unable to request reset button gpio\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_RESET_BUTTON);
+	if (ret < 0) {
+		printf("Unable to set reset button as input\n");
+		return -1;
+	}
+
+	/* Check if reset button is pressed for at least 3 seconds */
+	do {
+		if (gpio_get_value(NETBIRD_GPIO_RESET_BUTTON) != 0)  break;
+		udelay(100000);  /* 100ms */
+		counter++;
+
+		if (counter==30) {/* Indicate factory reset threshold */
+			/* let LED blink up once */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		} else if (counter==150) { /* Indicate recovery boot threshold */
+			/* let LED blink up twice */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		}
+	} while (counter<150);
+
+	if (counter < 30) return 0; /* Don't do anything for duration < 3s */
+
+	if (counter < 150) /* Do factory reset for duration between 3s and 15s */
+	{
+		char new_bootargs[512];
+		char *bootargs = getenv("bootargs");
+
+		if (bootargs==0) bootargs="";
+
+		printf("Do factory reset during boot...\n");
+
+		strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
+		strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
+
+		setenv("bootargs", new_bootargs);
+
+		printf("bootargs = %s\n", new_bootargs);
+
+		return 1;
+	} else {	/* Boot into recovery for duration > 15s */
+
+		/* set consoledev to external port */
+		setenv("consoledev", "ttyO0");
+
+		printf("Booting recovery image...\n");
+
+		/* Set bootcmd to run recovery */
+		setenv("bootcmd", "run recovery");
+
+		return 0;
+	}
+	return 0;
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_RST_GSM);
+	udelay(10000);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_PWR_GSM);
+	mdelay(1200);
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 0);
+	/* Enable debug LED to troubleshoot hw problems */
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_LED_A);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_LED_B);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_PHY_N);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_WLAN_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_BT_EN);
+	/* There are two funcions on the same mux mode for MMC2_DAT7 we want
+	 * to use RMII2_CRS_DV so we need to set SMA2 Register to 1
+	 * See SPRS717J site 49 (10)*/
+	#define SMA2_REGISTER (CTRL_BASE + 0x1320)
+	writel(0x01, SMA2_REGISTER); /* Select RMII2_CRS_DV instead of MMC2_DAT7 */
+
+	printf("OSC: %lu Hz\n", get_osclk());
+
+	return 0;
+}
+#if !defined(CONFIG_SPL_BUILD)
+
+static void set_devicetree_name(void)
+{
+	char devicetreename[64];
+	/* add hardware versions to environment */
+	if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
+		printf("Devicetree name not found, use legacy name\n");
+		strcpy(devicetreename, "am335x-nbhw16.dtb");
+	}
+
+	setenv("fdt_image", devicetreename);
+}
+
+static void get_hw_version(void)
+{
+	int hw_ver, hw_rev;
+	char hw_versions[16];
+	char new_env[256];
+
+	/* add hardware versions to environment */
+	bd_get_hw_version(&hw_ver, &hw_rev);
+	printf("HW16:  V%d.%d\n", hw_ver, hw_rev);
+	snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
+	snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
+	setenv("add_version_bootargs", new_env);
+}
+
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	int boot_partition;
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	/* add active root partition to environment */
+	boot_partition = bd_get_boot_partition();
+	if (boot_partition > 1) {
+		boot_partition = 0;
+	}
+
+	/* mmcblk1p1 => root0, mmcblk1p2 => root1 so +1 */
+	setenv_ulong("root_part", boot_partition + 1);
+
+	check_reset_button();
+
+	get_hw_version();
+
+	set_devicetree_name();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	int rc;
+	char *name = NULL;
+
+	set_board_info_env(name);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
+static void set_mac_address(int index, uchar mac[6])
+{
+	/* Then take mac from bd */
+	if (is_valid_ethaddr(mac)) {
+		eth_setenv_enetaddr_by_index("eth", index, mac);
+	}
+	else {
+		printf("Trying to set invalid MAC address");
+	}
+}
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr0[6] = {02,00,00,00,00,01};
+	uint8_t mac_addr1[6] = {02,00,00,00,00,02};
+	__maybe_unused struct ti_am_eeprom *header;
+
+#if !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+	cpsw_data.mdio_div = 0x3E;
+
+	bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
+	set_mac_address(0, mac_addr0);
+
+	bd_get_mac(1, mac_addr1, sizeof(mac_addr1));
+	set_mac_address(1, mac_addr1);
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[0].phy_addr = 0;
+	cpsw_slaves[1].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr0))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif

board/nm/netbird/board.h

@@ -0,0 +1,27 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif

board/nm/netbird/mux.c

@@ -0,0 +1,227 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+
+
+static struct module_pin_mux uart0_netbird_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart1_netbird_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd.uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},				/* (D15) uart1_txd.uart1_txd */
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D18) uart1_ctsn.uart1_ctsn */
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN | PULLUP_EN)},				/* (D17) uart1_rtsn.uart1_rtsn */
+	{-1},
+};
+
+static struct module_pin_mux rmii0_netbird_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS },			/* MII1_TXEN */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS },			/* MII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS },			/* MII1_TXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE },	/* MII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE },	/* MII1_RXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},	/* RMII1_REFCLK */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS },	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE }, /* MDIO_DATA */
+	{OFFSET(xdma_event_intr0), MODE(3) }, /* CLK_OUT1 for MDIO (design option) */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_netbird_pin_mux[] = {
+	{OFFSET(gpmc_a9), MODE(3) | PULLUDDIS | RXACTIVE},		/* MII2_CRS */
+	{OFFSET(gpmc_wpn), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII2_RXERR */
+	{OFFSET(gpmc_a0), MODE(3) | PULLUDDIS},			/* MII2_TXEN */
+	{OFFSET(gpmc_a5), MODE(3) | PULLUDDIS},			/* MII2_TXD0 */
+	{OFFSET(gpmc_a4), MODE(3) | PULLUDDIS},			/* MII2_TXD1 */
+	{OFFSET(gpmc_a11), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(gpmc_a10), MODE(3) | PULLUDDIS | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_col), MODE(1) | PULLUDDIS | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux gpio_netbird_pin_mux[] = {
+	/* Bank 0 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */  /* PWM */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},	/* (J18) gmii1_txd3.gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* (U12) gpmc_ad11.gpio0[27] */  /* RST_EXT~ */
+	/* Bank 1 */
+	{OFFSET(gpmc_ad13), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R12) gpmc_ad13.gpio1[13] */  /* BUTTON */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},	/* (V13) gpmc_ad14.gpio1[14] */  /* LED_A */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)},	/* (U13) gpmc_ad15.gpio1[15] */  /* LED_B */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* (U15) gpmc_a6.gpio1[22] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},	/* (V16) gpmc_a8.gpio1[24] */  /* RST_GSM~ */
+	/* Bank 2 */
+	{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)},	/* (V5) lcd_pclk.gpio2[24] */  /* EN_GPS_ANT */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[9] */  /* SYSBOOT */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[10] */  /* SYSBOOT */
+	/* Bank 3 */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (J17) gmii1_rxdv.gpio3[4] */  /* BT_EN */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (K18) gmii1_txclk.gpio3[9] */  /* WLAN_IRQ */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (L18) gmii1_rxclk.gpio3[10] */  /* WLAN_EN */
+	{-1},
+};
+
+static struct module_pin_mux usb_netbird_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN | PULLDOWN_EN)},	/* (F16) USB0_DRVVBUS.USB0_DRVVBUS */  /* PWM */
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F15) USB1_DRVVBUS.USB1_DRVVBUS */  /* RST_PHY~ */
+	{-1},
+};
+
+static struct module_pin_mux unused_netbird_pin_mux[] = {
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT6 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT7 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT10 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT11 is not used bulldown active, receiver disabled */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_netbird_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_netbird_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles.  These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE	0x0
+#define PROFILE_0	(1 << 0)
+#define PROFILE_1	(1 << 1)
+#define PROFILE_2	(1 << 2)
+#define PROFILE_3	(1 << 3)
+#define PROFILE_4	(1 << 4)
+#define PROFILE_5	(1 << 5)
+#define PROFILE_6	(1 << 6)
+#define PROFILE_7	(1 << 7)
+#define PROFILE_MASK	0x7
+#define PROFILE_ALL	0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR	0x35
+#define CFG_REG		0x10
+
+void enable_board_pin_mux(void)
+{
+	/* Netbird board */
+	configure_module_pin_mux(gpio_netbird_pin_mux);
+	configure_module_pin_mux(rmii0_netbird_pin_mux);
+	configure_module_pin_mux(rmii1_netbird_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(unused_netbird_pin_mux);
+}

board/nm/netbird/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/netbird/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/netbird_v2/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NETBIRD_V2
+
+config SYS_BOARD
+        default "netbird_v2"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_netbird_v2"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/netbird_v2/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o shield.o shield_can.o shield_comio.o fileaccess.o

board/nm/netbird_v2/board.c

@@ -0,0 +1,830 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <serial.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65218.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "../common/bdparser.h"
+#include "../common/board_descriptor.h"
+#include "board.h"
+#include "shield.h"
+#include "shield_can.h"
+#include "shield_comio.h"
+#include "fileaccess.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+
+#define NETBIRD_GPIO_RST_PHY_N	GPIO_TO_PIN(0, 16)
+#define NETBIRD_GPIO_PWR_GSM	GPIO_TO_PIN(1, 21)
+#define NETBIRD_GPIO_SUPPLY_GSM	GPIO_TO_PIN(0, 31)
+#define NETBIRD_GPIO_RST_GSM	GPIO_TO_PIN(1, 25)
+#define NETBIRD_GPIO_WLAN_EN	GPIO_TO_PIN(3, 10)
+#define NETBIRD_GPIO_BT_EN		GPIO_TO_PIN(3, 4)
+#define NETBIRD_GPIO_EN_GPS_ANT	GPIO_TO_PIN(2, 24)
+#define NETBIRD_GPIO_LED_A		GPIO_TO_PIN(1, 14)
+#define NETBIRD_GPIO_LED_B		GPIO_TO_PIN(1, 15)
+#define NETBIRD_GPIO_RESET_BUTTON	GPIO_TO_PIN(0, 2)
+#define NETBIRD_GPIO_USB_PWR_EN		GPIO_TO_PIN(1, 27)
+#define NETBIRD_GPIO_USB_PWR_EN_2	GPIO_TO_PIN(2, 4) // On new version this gpio is used
+
+#define DDR3_CLOCK_FREQUENCY (400)
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+
+#define BD_EEPROM_ADDR			(0x50)	/* CPU BD EEPROM (8kByte) is at 50 (A0) */
+#define BD_ADDRESS				(0x0000)  /* Board descriptor at beginning of EEPROM */
+#define PD_ADDRESS				(0x0200)  /* Product descriptor */
+#define PARTITION_ADDRESS		(0x0600)  /* Partition Table */
+
+static BD_Context   bdctx[3];		/* The descriptor context */
+
+
+static int _bd_init(void)
+{
+	if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
+		printf("%s() no valid bd found\n", __func__);
+		return -1;
+	}
+
+	if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
+		printf("%s() no valid pd found (legacy support)\n", __func__);
+	}
+
+	if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
+		printf("%s() no valid partition table found\n", __func__);
+	}
+
+	bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
+	return 0;
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static inline int __maybe_unused read_eeprom(void)
+{
+	return _bd_init();
+}
+
+struct serial_device *default_serial_console(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_UART) {
+		enable_uart0_pin_mux();
+		return &eserial1_device;
+	}
+	else {
+		return &eserial2_device;
+	}
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+static const struct ddr_data ddr3_netbird_data = {
+	/* Ratios were optimized by DDR3 training software from TI */
+	.datardsratio0 = 0x39,
+	.datawdsratio0 = 0x3f,
+	.datafwsratio0 = 0x98,
+	.datawrsratio0 = 0x7d,
+};
+
+static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_netbird_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = 0x61A,	/* 32ms > 85°C */
+	.sdram_tim1 = 0x0AAAE51B,
+	.sdram_tim2 = 0x246B7FDA,
+	.sdram_tim3 = 0x50FFE67F,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	env_init();
+	env_relocate_spec();
+	if (getenv_yesno("boot_os") != 1)
+		return 1;
+#endif
+
+	return 0;
+}
+#endif
+
+#define OSC	(V_OSCK/1000000)
+struct dpll_params dpll_ddr_nbhw16= {
+		DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CPU speed to 600 MHZ */
+	dpll_mpu_opp100.m = MPUPLL_M_600;
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Clear th PFM Flag on DCDC4 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_DCDC4, 0x00, 0x80)) {
+		puts ("tps65218_reg_write failure (DCDC4 clear PFM Flag)\n");
+	};
+
+	/* Disable DCDC2 because it is not used and could make noise */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE1, 0, 0x02)) {
+		puts ("tps65218_reg_write failure (DCDC2 disable)\n");
+	};
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	dpll_ddr_nbhw16.n = (get_osclk() / 1000000) - 1;
+	return &dpll_ddr_nbhw16;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_disabled_pin_mux();
+	enable_uart1_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+
+const struct ctrl_ioregs ioregs_netbird = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+
+void sdram_init(void)
+{
+	config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
+		   &ddr3_netbird_data,
+		   &ddr3_netbird_cmd_ctrl_data,
+		   &ddr3_netbird_emif_reg_data, 0);
+}
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+static void request_and_set_gpio(int gpio, char *name, int value)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, value);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLEAR_GPIO(N)	request_and_set_gpio(N, #N, 0);
+
+
+int check_reset_button(void)
+{
+	int counter = 0;
+	int ret;
+
+	ret = gpio_request(NETBIRD_GPIO_RESET_BUTTON, "reset button");
+	if (ret < 0) {
+		printf("Unable to request reset button gpio\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_RESET_BUTTON);
+	if (ret < 0) {
+		printf("Unable to set reset button as input\n");
+		return -1;
+	}
+
+	/* Check if reset button is pressed for at least 2 seconds ≃ ~5s */
+	do {
+		if (gpio_get_value(NETBIRD_GPIO_RESET_BUTTON) != 0)  break;
+		udelay(100000);  /* 100ms */
+		counter++;
+
+		if (counter==20) {/* Indicate factory reset threshold */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			/* let LED blink up once */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		} else if (counter==120) { /* Indicate recovery boot threshold */
+			/* let LED blink up twice */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 1);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 1);
+			udelay(400000);  /* 400ms */
+			gpio_set_value(NETBIRD_GPIO_LED_A, 0);
+			gpio_set_value(NETBIRD_GPIO_LED_B, 0);
+		}
+	} while (counter<120);
+
+	if (counter < 20) return 0; /* Don't do anything for duration < 2s */
+
+	if (counter < 120) /* Do factory reset for duration between ~5s and ~15s */
+	{
+		char new_bootargs[512];
+		char *bootargs = getenv("bootargs");
+
+		if (bootargs==0) bootargs="";
+
+		printf("Do factory reset during boot...\n");
+
+		strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
+		strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
+
+		setenv("bootargs", new_bootargs);
+
+		printf("bootargs = %s\n", new_bootargs);
+
+		return 1;
+	} else {	/* Boot into recovery for duration > 15s */
+		/* set consoledev to external port */
+		setenv("consoledev", "ttyS1");
+
+		printf("Booting recovery image...\n");
+
+		/* Set bootcmd to run recovery */
+		setenv("bootcmd", "run recovery");
+
+		return 0;
+	}
+	return 0;
+}
+
+static void enable_ext_usb(void)
+{
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_USB_PWR_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_USB_PWR_EN_2);
+	/* Disable LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE2, 0x00, 0x04)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+
+	/* Discharge LS2 to have proper 0V at the output */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG3, 0x02, 0x02)) {
+		puts ("tps65218_reg_write failure (LS2 discharge)\n");
+	};
+
+	mdelay(10);
+
+	gpio_set_value(NETBIRD_GPIO_USB_PWR_EN, 1);
+	gpio_set_value(NETBIRD_GPIO_USB_PWR_EN_2, 1);
+
+	mdelay(50);
+
+	/* Disable discharge LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG3, 0x00, 0x02)) {
+		puts ("tps65218_reg_write failure (LS2 discharge)\n");
+	};
+
+	/* Configure 500mA on LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_CONFIG2, 0x02, 0x03)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+
+	/* Enable LS2 */
+	if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_ENABLE2, 0x04, 0x04)) {
+		puts ("tps65218_reg_write failure (LS2 enable)\n");
+	};
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+
+	/* Remove power, and make sure reset is set once */
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_SUPPLY_GSM);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_GSM);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_PWR_GSM);
+	mdelay(20);
+	/* Enable gsm supply */
+	gpio_set_value(NETBIRD_GPIO_SUPPLY_GSM, 1);
+	mdelay(20);
+	/* Take modem out of reset, we have to wait 300ms afterwards */
+	gpio_set_value(NETBIRD_GPIO_RST_GSM, 0);
+	mdelay(300);
+	/* Do power up sequence, this modem has a special power up sequence
+	 * where we have to pull PWR for > 1s but < 7s (see manual) */
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 1);
+	mdelay(1200);
+	gpio_set_value(NETBIRD_GPIO_PWR_GSM, 0);
+
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_LED_A);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_LED_B);
+	REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_PHY_N);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_WLAN_EN);
+	REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_BT_EN);
+
+	/* There are two funcions on the same mux mode for MMC2_DAT7 we want
+	 * to use RMII2_CRS_DV so we need to set SMA2 Register to 1
+	 * See SPRS717J site 49 (10)*/
+	#define SMA2_REGISTER (CTRL_BASE + 0x1320)
+	writel(0x01, SMA2_REGISTER); /* Select RMII2_CRS_DV instead of MMC2_DAT7 */
+
+	enable_ext_usb();
+
+	printf("OSC:   %lu Hz\n", get_osclk());
+
+	return 0;
+}
+
+/* Enable the ecap2 pwm see siemens/pxm2 */
+static int enable_pwm(void)
+{
+#define PWM_TICKS	0xBEB
+#define PWM_DUTY	0x5F5
+#define AM33XX_ECAP2_BASE 0x48304100
+#define PWMSS2_BASE 0x48304000
+	struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS2_BASE;
+	struct pwmss_ecap_regs *ecap;
+	int ticks = PWM_TICKS;
+	int duty = PWM_DUTY;
+
+	ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP2_BASE;
+	/* enable clock */
+	setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
+	/* TimeStamp Counter register */
+	writel(0x0, &ecap->ctrphs);
+
+	setbits_le16(&ecap->ecctl2,
+			 (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK));
+
+	/* config period */
+	writel(ticks - 1, &ecap->cap3);
+	writel(ticks - 1, &ecap->cap1);
+	/* config duty */
+	writel(duty, &ecap->cap2);
+	writel(duty, &ecap->cap4);
+	/* start */
+	setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
+	return 0;
+}
+
+/* Enable the input clock for ecap2 and then enable the pwm */
+static void enable_wlan_clock(void)
+{
+	struct cm_perpll *const cmper = (struct cm_perpll*)CM_PER;
+	struct ctrl_dev *const cdev= (struct ctrl_dev*)CTRL_DEVICE_BASE;
+	u32 *const clk_domains[] = { 0 };
+
+	u32 *const clk_modules_nmspecific[] = {
+		&cmper->epwmss2clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains, clk_modules_nmspecific, 1);
+
+	/* Enable timebase clock for pwmss2 */
+	writel(0x04, &cdev->pwmssctrl);
+
+	enable_pwm();
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+void set_console(void)
+{
+	char buf[8];
+	char *defaultconsole = getenv("defaultconsole");
+	int shield_id = bd_get_shield(0);
+
+	if (defaultconsole == 0) {
+		/* Use the default console */
+		setenv("defaultconsole", "ttyS1");
+	}
+
+	/* Don't allow changing to ttyS0 because ttyS0 is not available in the
+	 * kernel if no comio shield is available */
+	if (shield_id != SHIELD_COM_IO) {
+		return;
+	}
+
+	/* With comio shield the defaultconsole should be ttyS0 and not ttyS1 */
+	setenv("defaultconsole", "ttyS0");
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (read_file("/root/boot/consoledev", buf, 5) != 5) {
+		puts("Invalid file consoledev\n");
+		return;
+	}
+
+	if (strstr(buf, "tty")==buf) {
+		buf[5] = 0;
+		setenv("defaultconsole", buf);
+	}
+}
+
+static void set_devicetree_name(void)
+{
+	char devicetreename[64];
+	/* add hardware versions to environment */
+	if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
+		printf("Devicetree name not found, use legacy name\n");
+		strcpy(devicetreename, "am335x-nbhw16-prod2.dtb");
+	}
+
+	setenv("fdt_image", devicetreename);
+}
+
+static void get_hw_version(void)
+{
+	int hw_ver, hw_rev;
+	char hw_versions[16];
+	char new_env[256];
+
+	/* add hardware versions to environment */
+	bd_get_hw_version(&hw_ver, &hw_rev);
+	printf("HW16:  V%d.%d\n", hw_ver, hw_rev);
+	snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
+	snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
+	setenv("add_version_bootargs", new_env);
+}
+
+static void check_fct(void)
+{
+	/* If probe fails we are sure no eeprom is connected */
+	if (i2c_probe(0x51) == 0) {
+		printf("Entering fct mode\n");
+		setenv ("bootcmd", "");
+	}
+}
+
+
+static void set_fdtshieldcmd(const char *fdt_cmd)
+{
+	setenv("fdtshieldcmd", fdt_cmd);
+}
+
+struct shield_command {
+	int shield_id;
+	const char *name;
+	const char *default_shieldcmd;
+	const char *fdtshieldcmd;
+	void (*init)(void);
+};
+
+static struct shield_command known_shield_commands[] = {
+	{
+		SHIELD_COM_IO,
+		"comio",
+		"shield comio mode rs232",
+		"fdt get value serial0 /aliases serial0;" \
+		"fdt set $serial0 status okay",
+		comio_shield_init
+	},
+	{
+		SHIELD_DUALCAN,
+		"dualcan",
+		"shield dualcan termination off off",
+		"fdt get value can0 /aliases d_can0;" \
+		"fdt get value can1 /aliases d_can1;" \
+		"fdt set $can0 status okay;" \
+		"fdt set $can1 status okay;",
+		can_shield_init
+	},
+	{
+		SHIELD_DUALCAN_PASSIVE,
+		"dualcan",
+		"shield dualcan termination off off",
+		"fdt get value can0 /aliases d_can0;" \
+		"fdt get value can1 /aliases d_can1;" \
+		"fdt set $can0 status okay;" \
+		"fdt set $can1 status okay;",
+		can_shield_init
+	}
+};
+
+static const struct shield_command* get_shield_command(int shield_id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(known_shield_commands); i++) {
+		if (known_shield_commands[i].shield_id == shield_id) {
+			return &known_shield_commands[i];
+		}
+	}
+
+	return NULL;
+}
+
+static void shield_config(void)
+{
+#define MAX_SHIELD_CMD_LEN 128
+	char shieldcmd_linux[MAX_SHIELD_CMD_LEN];
+	const char *shieldcmd;
+	const struct shield_command *cmd;
+	int len;
+
+	int shield_id = bd_get_shield(0);
+	if (shield_id < 0) {
+		debug("No shield found in bd\n");
+		return;
+	}
+
+	cmd = get_shield_command(shield_id);
+	if (cmd == NULL) {
+		printf ("Unknown shield id %d\n", shield_id);
+		return;
+	}
+
+	printf("Shield: %s\n", cmd->name);
+
+	cmd->init();
+	shieldcmd = cmd->default_shieldcmd;
+
+	/* If a shield configuration set by linux take it without bd check, we asume that Linux knows
+	 * what to do. */
+	len = read_file("/root/boot/shieldcmd", shieldcmd_linux, MAX_SHIELD_CMD_LEN);
+	if (len > 0) {
+		debug("Shield command found in file, using it\n");
+		shieldcmd = shieldcmd_linux;
+	}
+
+	setenv("shieldcmd", shieldcmd);
+
+	set_fdtshieldcmd(cmd->fdtshieldcmd);
+}
+
+static void shield_init(void)
+{
+	shield_config();
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	int boot_partition;
+
+	if (read_eeprom() < 0)
+		puts("Could not get board ID.\n");
+
+	/* add active root partition to environment */
+	boot_partition = bd_get_boot_partition();
+	if (boot_partition > 1) {
+		boot_partition = 0;
+	}
+
+	/* mmcblk1p1 => root0, mmcblk1p2 => root1 so +1 */
+	setenv_ulong("root_part", boot_partition + 1);
+
+	check_reset_button();
+
+	get_hw_version();
+
+	set_devicetree_name();
+
+	set_console();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	int rc;
+	char *name = NULL;
+
+	set_board_info_env(name);
+#endif
+
+	enable_wlan_clock();
+
+#if !defined(CONFIG_SPL_BUILD)
+	shield_init();
+
+	check_fct();
+
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
+static void set_mac_address(int index, uchar mac[6])
+{
+	/* Then take mac from bd */
+	if (is_valid_ethaddr(mac)) {
+		eth_setenv_enetaddr_by_index("eth", index, mac);
+	}
+	else {
+		printf("Trying to set invalid MAC address");
+	}
+}
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr0[6] = {02,00,00,00,00,01};
+	__maybe_unused struct ti_am_eeprom *header;
+
+#if !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+	cpsw_data.mdio_div = 0x3E;
+
+	bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
+	set_mac_address(0, mac_addr0);
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_slaves[0].phy_addr = 0;
+	cpsw_slaves[1].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr0))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif

board/nm/netbird_v2/board.h

@@ -0,0 +1,30 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart0_disabled_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#endif

board/nm/netbird_v2/fileaccess.c

@@ -0,0 +1,43 @@
+#include <common.h>
+#include <fs.h>
+
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	/* File does not exist, do not print an error message */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* If consoldev is set take this as productive conosle instead of default console */
+	if (fs_set_blk_dev("mmc", OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}
+

board/nm/netbird_v2/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/netbird_v2/mux.c

@@ -0,0 +1,229 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux uart0_disabled_netbird_pin_mux[] = {
+    /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE )},	/* (E18) UART0_CTSN */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN )},			/* (E17) UART0_RTSN */
+	{-1},
+};
+
+static struct module_pin_mux uart0_netbird_pin_mux[] = {
+    /* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux uart1_netbird_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd.uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* (D15) uart1_txd.uart1_txd */
+	{-1},
+};
+
+/* V2OK */
+static struct module_pin_mux rmii1_netbird_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},		    /* (H17) mii1_crs.rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE},		    /* (J15) mii1_rxerr.rmii1_rxerr */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS },			    /* (J16) mii1_txen.rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS },			    /* (K17) mii1_txd0.rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS },			    /* (K16) mii1_txd1.rmii1_txd1 */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE },		    /* (M16) mii1_rxd0.rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE },		    /* (L15) mii1_rxd1.rmii1_rxd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},		    /* (H18) rmii1_refclk.rmii1_refclk */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS },			    /* (M18) mdio_clk.mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE },    /* (M17) mido_data.mdio_data */
+	{OFFSET(xdma_event_intr0), MODE(3) },				    /* (A15) xdma_event_intr0.clkout1 (25 MHz clk for MDIO) */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)},			/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC0_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )},	/* MMC1_DAT3 */
+	{-1},
+};
+
+static struct module_pin_mux gpio_netbird_pin_mux[] = {
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (A17) spi0_sclk.gpio0[2] */  /* BUTTON */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */  /* PWM */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},	/* (J18) gmii1_txd3.gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* (U12) gpmc_ad11.gpio0[27] */  /* RST_EXT~ */
+	/* Bank 1 */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},	/* (V13) gpmc_ad14.gpio1[14] */  /* LED_A */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)},	/* (U13) gpmc_ad15.gpio1[15] */  /* LED_B */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (V17) gpmc_a11.gpio1[27] */  /* USB_PWR_EN */
+	{OFFSET(gpmc_a9),   (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (U16) gpmc_a9.gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (U17) gpmc_csn3.gpio0[31] */  /* GSM_SUPP_EN */
+	{OFFSET(gpmc_a5),   (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (V15) gpmc_a5.gpio1[21] */  /* GSM_PWR_EN */
+	/* Bank 2 */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[9] */  /* SYSBOOT */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN| PULLUP_EN)},	/* (V5) lcd_pclk.gpio2[10] */  /* SYSBOOT */
+	/* Bank 3 */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},	/* (J17) gmii1_rxdv.gpio3[4] */  /* BT_EN */
+	{OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},	/* (K18) gmii1_txclk.gpio3[9] */  /* WLAN_IRQ */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},	/* (L18) gmii1_rxclk.gpio3[10] */  /* WLAN_EN */
+	{OFFSET(mcasp0_ahclkr), (MODE(4) | PULLUDEN | PULLUP_EN)},	/* (C12) mcasp0_ahclkr.ecap2_in_pwm2_out */  /* WLAN_CLK */
+	{-1},
+};
+
+static struct module_pin_mux usb_netbird_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F16) USB0_DRVVBUS.USB0_DRVVBUS */  /* PWM */
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)},	/* (F15) USB1_DRVVBUS.USB1_DRVVBUS */  /* RST_PHY~ */
+	{-1},
+};
+
+static struct module_pin_mux unused_netbird_pin_mux[] = {
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT6 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT7 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT10 is not used bulldown active, receiver disabled */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* SYSBOOT11 is not used bulldown active, receiver disabled */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_netbird_pin_mux);
+}
+
+void enable_uart0_disabled_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_netbird_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_netbird_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles.  These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE	0x0
+#define PROFILE_0	(1 << 0)
+#define PROFILE_1	(1 << 1)
+#define PROFILE_2	(1 << 2)
+#define PROFILE_3	(1 << 3)
+#define PROFILE_4	(1 << 4)
+#define PROFILE_5	(1 << 5)
+#define PROFILE_6	(1 << 6)
+#define PROFILE_7	(1 << 7)
+#define PROFILE_MASK	0x7
+#define PROFILE_ALL	0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR	0x35
+#define CFG_REG		0x10
+
+void enable_board_pin_mux(void)
+{
+	/* Netbird board */
+	configure_module_pin_mux(gpio_netbird_pin_mux);
+	configure_module_pin_mux(rmii1_netbird_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
+	configure_module_pin_mux(usb_netbird_pin_mux);
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(unused_netbird_pin_mux);
+}

board/nm/netbird_v2/shield.c

@@ -0,0 +1,73 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define MAX_SHIELDS 16
+
+static struct shield_t *shields[MAX_SHIELDS];
+static int shield_count = 0;
+
+/* Perhaps this function shouldn't leave in shields.c? */
+int shield_gpio_request_as_input(unsigned int gpio, const char *label)
+{
+	int ret;
+
+ 	ret = gpio_request(gpio, label);
+	if ((ret < 0)) {
+		printf("Could not request shield slot %s gpio\n", label);
+		return -1;
+	}
+
+	ret = gpio_direction_input(gpio);
+	if ((ret < 0)) {
+		printf("Could not configure shield slot %s gpio as input\n", label);
+		return -1;
+	}
+
+	return 0;
+}
+
+void shield_register(struct shield_t *shield)
+{
+	if (shield_count >= MAX_SHIELDS) {
+		printf("Max shield count reached (%d), please increment MAX_SHIELDS\n", MAX_SHIELDS);
+		return;
+	}
+	shields[shield_count++] = shield;
+}
+
+int shield_set_mode(const char* shield_type, int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < shield_count; i++) {
+		if (strcmp(shield_type, shields[i]->name) == 0) {
+			return shields[i]->setmode(argv, argc);
+		}
+	}
+	printf("## Error: No %s shield installed\n", shield_type);
+	/* Do not return error, to not show usage (request by rs) */
+	return 0;
+}
+
+static int do_shieldmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		return -1;
+	}
+
+	return shield_set_mode(argv[1], argc - 2, &argv[2]);
+}
+
+U_BOOT_CMD(
+	shield,	6,	1,	do_shieldmode,
+	"Set the shield mode",
+	"dualcan termination [on|off] [on|off]\n"
+	"shield comio mode [rs232|rs485] termination [on|off]\n"
+);
+

board/nm/netbird_v2/shield.h

@@ -0,0 +1,26 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/shield.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Wed 31 May 2017 02:56:16 PM CEST \n
+ * 	Last Update:	Wed 31 May 2017 02:56:16 PM CEST
+ */
+#ifndef SHIELD_H
+#define SHIELD_H
+
+#define SHIELD_COM_IO		0
+#define SHIELD_DUALCAN		1
+#define SHIELD_CAN_GNSS		2
+#define SHIELD_DUALCAN_PASSIVE	3
+
+struct shield_t{
+    char name[64];
+    int (*setmode)(char * const argv[], int argc);
+};
+
+int shield_setmode(int mode);
+void shield_register(struct shield_t *shield);
+
+int shield_gpio_request_as_input(unsigned int gpio, const char *label);
+
+#endif // SHIELD_H

board/nm/netbird_v2/shield_can.c

@@ -0,0 +1,193 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LATCH GPIO_TO_PIN(0, 7)
+#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 10)
+#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 8)
+
+
+static int shield_slot_initialized = 0;
+
+
+static struct module_pin_mux can_shield_netbird_pin_mux_config[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* CAN1 tx */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* CAN0 tx */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* Latch EN */
+	{-1},
+};
+
+static struct module_pin_mux can_shield_netbird_pin_mux_final[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},	/* CAN1 tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},	/* CAN1 rx */
+	{OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)},	/* CAN0 rx */
+	{OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},			/* CAN0 tx */
+	{-1},
+};
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LATCH, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type dualcan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Configure shield pin muxing for configuration\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_config);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to high\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LATCH, 1);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to low\n");
+	gpio_set_value(NETBIRD_GPIO_LATCH, 0);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set final can shield muxing\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_final);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+#define CAN_PORTS	2
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	return (!terminations[0] << 0) | (!terminations[1] << 1);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 3) {
+		debug("Too few arguments for dualcan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+struct shield_t can_shield = {
+	"dualcan", set_shieldmode
+};
+
+void can_shield_init(void)
+{
+	shield_register(&can_shield);
+}
+

board/nm/netbird_v2/shield_can.h

@@ -0,0 +1,9 @@
+#ifndef SHIELD_CAN_H
+#define SHIELD_CAN_H
+
+int shield_can_init(void);
+int shield_can_setmode(int mode);
+
+void can_shield_init(void);
+
+#endif // SHIELD_CAN_H

board/nm/netbird_v2/shield_comio.c

@@ -0,0 +1,251 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define NETBIRD_GPIO_RST_SHIELD_N GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LOAD GPIO_TO_PIN(1, 9)
+#define NETBIRD_GPIO_MODE_0 GPIO_TO_PIN(1, 11)
+#define NETBIRD_GPIO_MODE_1 GPIO_TO_PIN(1, 10)
+
+
+static int shield_slot_initialized = 0;
+
+
+/* V2OK */
+static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux shield_gpio_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E16) UART0_TXD */
+	{-1},
+};
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Extension slot init\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LOAD, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug ("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type comio\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Enable gpio pull-ups\n");
+	configure_module_pin_mux(shield_gpio_netbird_pin_mux);
+
+	debug("Set load to low\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LOAD, 0);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set load to high\n");
+	gpio_set_value(NETBIRD_GPIO_LOAD, 1);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Disable pullups on shield gpios\n");
+	configure_module_pin_mux(shield_gpio_safe_netbird_pin_mux);
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set gpio load as input again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_LOAD);
+	if (ret < 0) {
+		puts("Can not configure shield slot load as input");
+		return -1;
+	}
+
+	return 0;
+}
+
+enum mode_nr {
+	RS232,
+	RS485,
+	UNKNOWN
+};
+
+struct mode {
+	enum mode_nr nr;
+	const char* name;
+	int argc;
+};
+
+struct mode modes[] = {
+	{RS232, "rs232", 0},
+	{RS485, "rs485", 2}
+};
+
+static const struct mode *get_mode(const char *mode)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		if (strcmp(modes[i].name, mode) == 0) {
+			return &modes[i];
+		}
+	}
+	return NULL;
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int termination = 0;
+	int rs232 = 0;
+	const struct mode *selected_mode;
+
+	assert(argc >= 2);
+
+	if (strcmp ("mode", argv[0])) {
+		debug("Invalid arguments (see help)\n");
+		return -1;
+	}
+
+	selected_mode = get_mode(argv[1]);
+	if (selected_mode == NULL) {
+		debug("Mode %s not supported\n", argv[1]);
+		return -1;
+	}
+
+	debug ("Mode %s, index %d, argc %d\n", selected_mode->name,
+			selected_mode->nr, selected_mode->argc);
+
+	if (selected_mode->argc != argc - 2) {
+		debug("Invalid argument count for mode %s (should %d is %d)\n",
+				argv[1],  selected_mode->argc, argc - 2);
+		return -1;
+	}
+
+	if (selected_mode->nr == RS485) {
+		if (strcmp("termination", argv[2])) {
+			debug("Invalid arguments, do not configure termination\n");
+			return -1;
+		}
+
+		termination = get_termination(argv[3]);
+		if (termination < 0) {
+			debug("Invalid termination %s\n", argv[3]);
+			return -1;
+		}
+	}
+	else {
+		rs232 = 1;
+	}
+
+	/* Termination is inverse */
+	return (rs232 << 0) | ((!termination) << 1);
+}
+
+int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc < 2) {
+		debug("Too few arguments for comio\n");
+		return -1;
+	}
+
+	/* -1 will make configure_shieldmode to faile and is okay therefore */
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+struct shield_t comio_shield = {
+	"comio", set_shieldmode
+};
+
+void comio_shield_init(void)
+{
+	shield_register(&comio_shield);
+}
+

board/nm/netbird_v2/shield_comio.h

@@ -0,0 +1,6 @@
+#ifndef SHIELD_COMIO_H
+#define SHIELD_COMIO_H
+
+void comio_shield_init(void);
+
+#endif // SHIELD_COMIO_H

board/nm/netbird_v2/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/netbird_v2/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/nmhw21/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NMHW21
+
+config SYS_BOARD
+        default "nmhw21"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_nmhw21"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 3
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/nmhw21/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o ../common/da9063.o ../common/ether_crc.o fileaccess.o sja1105.o ui.o um.o reset_reason.o

board/nm/nmhw21/board.h

@@ -0,0 +1,24 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_spi1_mux(void);
+void enable_led_mux(void);
+void enable_led_mux_v32(void);
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
+#endif

board/nm/nmhw21/fileaccess.c

@@ -0,0 +1,40 @@
+#include <common.h>
+#include <fs.h>
+
+#define BLOCK_DEVICE "mmc"
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	/* Read at most file size bytes */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}

board/nm/nmhw21/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/nmhw21/mux.c

@@ -0,0 +1,318 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* (V2)  GPIO0_8: RS232_485n_SEL (V3.2)
+	* (V3)  GPIO0_9: RS485_DE (V3.2)
+	* (J18) GPIO0_16: ETH_SW_RST~ (V2.0)
+	* (K15) GPIO0_17: CTRL.INT~
+	* (T10) GPIO0_23: CAN_TERM1~ (V1.0)
+	*
+	* (T12) GPIO1_12: SIM_SW
+	* (V13) GPIO1_14: GNSS_RST~
+	* (U13) GPIO1_15: CAN_TERM0~ (V1.0)
+	* (R14) GPIO1_20: BT_EN
+	* (V15) GPIO1_21: GSM_PWR_EN
+	* (U16) GPIO1_25: RST_GSM
+	* (T16) GPIO1_26: WLAN_EN
+	* (V17) GPIO1_27: WLAN_IRQ
+	*
+	* (U3) GPIO2_16: TIMEPULSE (HW26), see note [1]
+	* (R6) GPIO2_25: RST_ETH~
+	*
+	* (J17) GPIO3_4: GNSS_EXTINT
+	* (K18) GPIO3_9: CTRL.W_DIS
+	* (L18) GPIO3_10: CTRL.RST
+	* (C12) GPIO3_17: UI_RST~
+	* (A14) GPIO3_21: RST_HUB~ (USB)
+	*
+	* [1] No PU/PD allowed as TIMEPULSE is internally connected with SAFEBOOT_N.
+	*     SAFEBOOT_N must be left open/floating.
+	*/
+
+	/* Bank 0 */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) GPIO0_16: ETH_SW_RST~ (V2.0) */
+	{OFFSET(mii1_txd2), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (K15) GPIO0_17: CTRL.INT~ */
+	{OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)},				/* (T10) GPIO0_23: CAN_TERM1~ */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_ad12), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (T12) GPIO1_12: SIM_SW */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},				/* (V13) GPIO1_14: GNSS_RST~ */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)},				/* (U13) GPIO1_15: CAN_TERM0~ */
+
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},				/* (R14) gpio1_20: BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},				/* (V15) gpio1_21: GSM_PWR_EN */
+	{OFFSET(gpmc_a9), (MODE(7) | PULLUDDIS)},				/* (U16) gpio1_25: RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},				/* (T16) gpio1_26: WLAN_EN */
+	{OFFSET(gpmc_a11), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V17) gpio1_27: WLAN_IRQ */
+
+	/* Bank 2 */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (U3) GPIO2_16: TIMEPULSE */
+	{OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},			/* (R6) GPIO2_25: RST_ETH~ */
+
+	/* Bank 3 */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)},			/* (J17) GPIO3_4: GNSS_EXTINT */
+	{OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)},			/* (K18) GPIO3_9: CTRL.W_DIS */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},			/* (L18) GPIO3_10: CTRL.RST~ */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS)},			/* (C12) GPIO3_17: UI_RST~ */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDDIS)},			/* (A14) GPIO3_21: RST_HUB~ (USB) */
+	{-1}
+};
+
+static struct module_pin_mux led_pin_mux[] = {
+	/*
+	* (T17) GPIO0_30: LED0.GN
+	* (U15) GPIO1_22: LED1.RD
+	* (V16) GPIO1_24: LED1.GN
+	* (U18) GPIO1_28: LED0.RD
+	*/
+
+	{OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS)},				/* (T17) GPIO0_30: LED0.GN */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},				/* (U15) GPIO1_22: LED1.RD */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},				/* (V16) GPIO1_24: LED1.GN */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},				/* (U18) GPIO1_28: LED0.RD */
+	{-1}
+};
+
+static struct module_pin_mux led_pin_mux_v32[] = {
+	/*
+	* (C15) GPIO0_6: MB_LED_PWM
+	* (U15) GPIO1_22: LED1.RD
+	* (T15) GPIO1_23: LED0.GN (formerly: (T17) GPIO0_30)
+	* (V16) GPIO1_24: LED1.GN
+	* (U18) GPIO1_28: LED0.RD
+	*/
+
+	{OFFSET(spi0_cs1), (MODE(7) | PULLUDDIS)},				/* (C15) GPIO0_6: MB_LED_PWM */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},				/* (U15) GPIO1_22: LED1.RD */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUDDIS)},				/* (T15) GPIO1_23: LED0.GN */
+	{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)},				/* (V16) GPIO1_24: LED1.GN */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},				/* (U18) GPIO1_28: LED0.RD */
+	{-1}
+};
+
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1}
+};
+
+/* I2C1 System */
+static struct module_pin_mux i2c1_pin_mux[] = {
+	{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (A16) i2c_scl */
+	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (B16) i2c_sda */
+	{-1}
+};
+
+/* RMII1: Ethernet Switch */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for Switch) */
+	{-1}
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1}
+};
+
+
+/* TODO: SPI in operational mode */
+/* What in XModem SPL Boot */
+
+/* SPI1 */
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(4) | PULLUDEN | PULLUP_EN)},		/* (C18) spi1_clk */
+	{OFFSET(uart0_rtsn), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (E17) spi1_mosi */
+	{OFFSET(uart0_ctsn), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E18) spi1_miso */
+	{OFFSET(uart0_rxd), (MODE(1) | PULLUDEN | PULLUP_EN)},			/* (E15) spi1_cs0 */
+	{OFFSET(uart0_txd), (MODE(1) | PULLUDEN | PULLUP_EN)},			/* (E16) spi1_cs1 */
+	{-1}
+};
+
+/* CAN0: */
+static struct module_pin_mux can0_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(2) | RXACTIVE | PULLUDEN | PULLUP_EN)},	/* (D17) can0_rxd */
+	{OFFSET(uart1_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},			/* (D18) can0_txd */
+	{-1}
+};
+
+/* CAN1: */
+static struct module_pin_mux can1_pin_mux[] = {
+	{OFFSET(uart1_txd), (MODE(2) | RXACTIVE | PULLUDEN | PULLUP_EN)},	/* (D15) can1_rxd */
+	{OFFSET(uart1_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},			/* (D16) can1_txd */
+	{-1}
+};
+
+/* UART2: Debug/Console */
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (A17) uart2_rxd */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN | PULLUP_EN)},			/* (B17) uart2_txd */
+	{-1}
+};
+
+/* UART3: GNSS */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDDIS | RXACTIVE)},			/* (L17) UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDDIS | SLEWCTRL)},			/* (L16) UART3_TXD */
+	{-1}
+};
+
+/* UART4: User RS232/485 (V3.2 only) */
+static struct module_pin_mux uart4_pin_mux[] = {
+	/*
+	 * CTSn = SEL_RS232/RS485~: Default = Low -> RS485 mode
+	 * RTSn = RS485_DE: Default = Low -> RS485 transmitter disabled
+	 *        Configure as GPIO in U-Boot to keep disabled, Linux will change to RTSn
+	 */
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T17) UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (U17) UART4_TXD */
+	{OFFSET(lcd_data12), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (V2) uart4_ctsn */
+	{OFFSET(lcd_data13), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (V3) uart4_rtsn */
+	{-1}
+};
+
+/* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1}
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1}
+};
+
+/* UART0: <tbd> */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1}
+};
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+/*	configure_module_pin_mux(spi1_pin_mux); */
+	/* TODO: SPL Bringup */
+
+	configure_module_pin_mux(uart3_pin_mux);
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(can0_pin_mux);
+	configure_module_pin_mux(can1_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_spi1_mux(void)
+{
+	configure_module_pin_mux(spi1_pin_mux);
+}
+
+void enable_led_mux(void)
+{
+	configure_module_pin_mux(led_pin_mux);
+}
+
+void enable_led_mux_v32(void)
+{
+	configure_module_pin_mux(led_pin_mux_v32);
+}

board/nm/nmhw21/reset_reason.c

@@ -0,0 +1,81 @@
+/*
+ * reset_reason.c
+ *
+ * Reset/start reason handling
+ *
+ * Copyright (C) 2021 NetModule AG - https://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include "../common/ether_crc.h"
+#include "reset_reason.h"
+
+
+void rr_set_reset_reason(volatile struct reset_registers* reset_regs, uint32_t reason)
+{
+	reset_regs->rr_value = reason;
+	reset_regs->rr_value_crc = ether_crc(sizeof(reset_regs->rr_value),
+					     (const uint8_t*)&(reset_regs->rr_value));
+}
+
+bool rr_is_reset_reason_valid(volatile const struct reset_registers* reset_regs)
+{
+	const uint32_t crc = ether_crc(sizeof(reset_regs->rr_value), 
+				       (const uint8_t*)&(reset_regs->rr_value));
+	return crc == reset_regs->rr_value_crc;
+}
+
+void rr_set_start_reason(volatile struct reset_registers* reset_regs, uint32_t event)
+{
+	/* Store start events in shared memory region for OS */
+	reset_regs->sr_magic = SR_MAGIC;
+	reset_regs->sr_events = event;
+	reset_regs->sr_checksum = ether_crc(sizeof(reset_regs->sr_events),
+					    (const uint8_t*)&(reset_regs->sr_events));	
+}
+
+bool rr_is_start_reason_valid(volatile const struct reset_registers* reset_regs)
+{
+	if (reset_regs->sr_magic == SR_MAGIC) {
+		const uint32_t crc = ether_crc(sizeof(reset_regs->sr_events), 
+					(const uint8_t*)&(reset_regs->sr_events));
+		if (crc == reset_regs->sr_checksum) {
+			return true;
+		}
+	}
+	
+	return false;
+}
+
+void rr_start_reason_to_str(uint32_t events, char* buffer, size_t bufsize)
+{
+	if (events == 0) {
+		strncpy(buffer, "-\n", bufsize);
+	}
+	else {
+		buffer[0] = 0;
+		if (events & SR_POR)
+			strncat(buffer, "PowerOn, ", bufsize);
+		if (events & SR_WATCHDOG)
+			strncat(buffer, "Watchdog, ", bufsize);
+		if (events & SR_REBOOT)
+			strncat(buffer, "Reboot, ", bufsize);
+		if (events & SR_WAKEUP)
+			strncat(buffer, "Wakeup, ", bufsize);
+
+		if (events & SR_EVT_IGNITION)
+			strncat(buffer, "Ignition, ", bufsize);
+		if (events & SR_EVT_RTC_ALARM)
+			strncat(buffer, "RTC, ", bufsize);
+		if (events & SR_EVT_RTC_TICK)
+			strncat(buffer, "Tick, ", bufsize);
+		if (events & SR_EVT_GPI)
+			strncat(buffer, "GPI, ", bufsize);
+		if (events & SR_EVT_BUTTON)
+			strncat(buffer, "Button, ", bufsize);
+
+		/* Trim last comma, no 0 len check required, at least one entry is present */
+		buffer[strlen(buffer)-2] = 0;
+	}
+}

board/nm/nmhw21/reset_reason.h

@@ -0,0 +1,60 @@
+/*
+ * reset_reason.h
+ *
+ * Reset/start reason handling
+ *
+ * Copyright (C) 2021 NetModule AG - https://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef RESET_REASON_H
+#define RESET_REASON_H
+
+struct reset_registers {
+	/* Reboot Reasons, set by OS, expect watchdog set by bootloader */
+	uint32_t rr_value;
+	uint32_t rr_value_crc;
+
+	/* Start Reasons as determined by hardware */
+	uint32_t sr_magic;	/* Token to check presence of following fields */
+	uint32_t sr_events;	/* Events bitmask, see SE_... defines */
+	uint32_t sr_checksum;	/* Checksum over se_events */
+};
+
+/* Watchdog reboot reason event */
+#define RR_POWEROFF_PATTERN		0x00000000
+#define RR_EXTERNAL_WATCHDOG_PATTERN	0x781f9ce2
+#define RR_BOOT_PATTERN			0x424f4f54	/* ‘BOOT’, 0xb9808470 */
+#define RR_REBOOT_PATTERN		0x5245424f	/* ‘REBO’, 0x7d5d9d66 */
+#define RR_OOPS_PATTERN			0x4F4F5053	/* ‘OOPS’, 0x2b85bc5f */
+#define RR_WAKE_PATTERN			0x57414B45	/* 'WAKE', 0x7b0acb48 */
+
+/* Start reason token 'SRTE' */
+#define SR_MAGIC			0x53525445
+
+/* Possible start events (see sr_events) */
+#define SR_POR  			0x00000001
+#define SR_WATCHDOG  			0x00000010
+#define SR_REBOOT  			0x00000020
+#define SR_WAKEUP  			0x00000080	/* See SR_EVT_xx bits */
+
+/* In case of wake-up, these are the events that caused the start */
+#define SR_EVT_IGNITION  		0x00000100
+#define SR_EVT_RTC_ALARM  		0x00000200	/* RTC date/time alarm */
+#define SR_EVT_RTC_TICK  		0x00000400	/* RTC tick based alarm */
+#define SR_EVT_GPI			0x00000800	/* General purpose input(s) */
+#define SR_EVT_BUTTON			0x00001000	
+#define SR_EVT_WAKE_MASK		0x00001F00
+
+
+
+extern void rr_set_reset_reason(volatile struct reset_registers* reset_regs, uint32_t reason);
+extern bool rr_is_reset_reason_valid(volatile const struct reset_registers* reset_regs);
+
+extern void rr_set_start_reason(volatile struct reset_registers* reset_regs, uint32_t event);
+extern bool rr_is_start_reason_valid(volatile const struct reset_registers* reset_regs);
+extern void rr_start_reason_to_str(uint32_t events, char* buffer, size_t bufsize);
+
+
+#endif /* RESET_REASON_H */

board/nm/nmhw21/sja1105.c

@@ -0,0 +1,274 @@
+/*
+ * sja1105.c
+ *
+ * Functions for NXP SJA1105 Ethernet Switch
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spi.h>
+
+#include "sja1105.h"
+
+
+#define SJA_OPCODE_WRITE	0x80
+#define SJA_OPCODE_READ		0x00
+#define SJA_READ_CNT(x)		(((x) & 0x3F) << 1)
+
+
+
+static struct spi_slave *sja1105_spi_bus = 0;
+static int bus_claimed = 0;
+
+
+void sja1105_init(struct spi_slave *spi)
+{
+	sja1105_spi_bus = spi;
+}
+
+void sja1105_claim_bus(void)
+{
+	spi_claim_bus(sja1105_spi_bus);
+
+	bus_claimed++;
+}
+
+void sja1105_release_bus(void)
+{
+	spi_release_bus(sja1105_spi_bus);
+
+	bus_claimed--;
+}
+
+uint32_t sja1105_read_reg(uint32_t address)
+{
+	uint32_t return_value;
+	uint8_t dataspi[8];
+	uint8_t datain[8];
+
+	/* OPCODE: READ, READ CNT = 1, address from bit 24 DOWNTO bit 4 */
+
+	dataspi[0] = (SJA_OPCODE_READ | SJA_READ_CNT(1)) | ((address >> 20) & 0x01); /* MSB */
+	dataspi[1] = (address >> 12) & 0xFF;
+	dataspi[2] = (address >> 4) & 0xFF;
+	dataspi[3] = (address << 4) & 0xF0;
+
+	dataspi[4] = 0x00; /* ignored by slave, use to readout the register */
+	dataspi[5] = 0x00;
+	dataspi[6] = 0x00;
+	dataspi[7] = 0x00;
+
+	(void)spi_xfer(sja1105_spi_bus, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
+
+	return_value = (datain[4]<<24) | (datain[5]<<16) | (datain[6]<<8) | (datain[7]<<0);
+
+	return return_value;
+}
+
+void sja1105_write_reg(uint32_t address, uint32_t data)
+{
+	uint8_t dataspi[8];
+
+	/* OPCODE: WRITE, address from bit 24 DOWNTO bit 4 */
+
+	dataspi[0] = SJA_OPCODE_WRITE | (address >> 20 & 0x01);
+	dataspi[1] = (address >> 12) & 0xFF;/* */
+	dataspi[2] = (address >> 4) & 0xFF;
+	dataspi[3] = (address << 4) & 0xF0;
+
+	dataspi[4] = (data >> 24) & 0xFF;
+	dataspi[5] = (data >> 16) & 0xFF;
+	dataspi[6] = (data >> 8) & 0xFF;
+	dataspi[7] = data & 0xFF;
+
+	(void)spi_xfer(sja1105_spi_bus, 8*sizeof(dataspi) /*bitlen*/, dataspi, NULL /*din*/, SPI_XFER_BEGIN| SPI_XFER_END /*flags*/);
+}
+
+void sja1105_configure_firmware(void)
+{
+    static const uint8_t config_data_0[] = { 0x80, 0x20, 0x00, 0x00, 0x9E, 0x00, 0x03, 0x0E, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x21, 0x6F, 0x25, 0x6B, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF };
+    static const uint8_t config_data_1[] = { 0x80, 0x20, 0x04, 0x00, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF9, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0x03, 0x68, 0x8B, 0xEA, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x7D, 0x0B, 0xCB, 0xF2, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x31, 0x80, 0x7F, 0x09, 0x52, 0x68, 0x0D, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1A, 0x6A, 0xF6, 0x23, 0x53, 0x10, 0x00, 0x00, 0x00, 0xF7, 0xBD, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xEF, 0x7B, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xDE, 0xF7, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xBD, 0xEF, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0x7B, 0xDF, 0xF5, 0x8D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x04, 0xA6, 0x06, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0xDA, 0xB5, 0xBD, 0xC8, 0x00, 0x3F, 0xFC, 0x08, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
+    static const uint8_t config_data_2[] = { 0x80, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFC, 0x08, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFC, 0x08, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFC, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFC, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x83, 0x75, 0xF9, 0x8D, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x25, 0x0E, 0x7C, 0xBD, 0x00, 0x01, 0x25, 0xC0, 0x70, 0x94, 0x84, 0x50, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC8, 0xA7, 0xCE, 0xE6, 0x00, 0x71, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0xF7, 0x04, 0xB9, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x57, 0x1F, 0x81, 0x3F, 0x06, 0x44, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0D, 0xB0, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x5A, 0x9C, 0x37, 0x20, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x3A, 0x5D, 0x5E, 0x24, 0xA4, 0x9A, 0x00, 0x00, 0x7B, 0x51, 0xDA, 0x7D, 0x00, 0x00, 0x00, 0x00 };
+    static const uint8_t config_data_3[] = { 0x80, 0x20, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x37, 0x6E, 0x02, 0x8B };
+
+	uint32_t val;
+	int rc;
+
+	rc = spi_xfer(sja1105_spi_bus, 8*sizeof(config_data_0) /*bitlen*/, config_data_0, NULL, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
+	if (rc != 0)
+		printf ("spi_xfer fail for config data 0\n");
+
+	rc = spi_xfer(sja1105_spi_bus, 8*sizeof(config_data_1) /*bitlen*/, config_data_1, NULL, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
+	if (rc != 0)
+		printf ("spi_xfer fail for config data 1\n");
+
+	rc = spi_xfer(sja1105_spi_bus, 8*sizeof(config_data_2) /*bitlen*/, config_data_2, NULL, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
+	if (rc != 0)
+		printf ("spi_xfer fail for config data 2\n");
+
+	rc = spi_xfer(sja1105_spi_bus, 8*sizeof(config_data_3) /*bitlen*/, config_data_3, NULL, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
+	if (rc != 0)
+		printf ("spi_xfer fail for config data 3\n");
+
+	/* Check that config was properly loaded */
+	val = sja1105_read_reg(SJA_REG_CONFIG_STATUS);
+	if ((val & 0x80000000) != 0x80000000) { // TODO: Define bitmask
+		printf("ERROR: Switch configuration load failed\n");
+
+		// TODO: provide return code.
+	}
+}
+
+void sja1105_configure_mode_and_clocks(void)
+{
+	sja1105_write_reg( 0x10000A, 0x0A010141);	/* PLL 1 setup for 50MHz */
+	sja1105_write_reg( 0x10000A, 0x0A010940);	/* PLL 1 setup for 50MHz */
+
+	/* Port 0:  RMII (PHY mode = external REFCLK) */
+	sja1105_write_reg( 0x10000B, 0x0A000001);	// Disable IDIV0
+	sja1105_write_reg( 0x100015, 0x00000800);	// CLKSRC of RMII_REF_CLK_0 = TX_CLK_0
+
+	/* Port 1: RMII (MAC mode) */
+	sja1105_write_reg( 0x10000C, 0x0A000001);	// Disable IDIV1
+	sja1105_write_reg( 0x10001C, 0x02000800);	// CLKSRC of RMII_REF_CLK_1 = TX_CLK_1
+	sja1105_write_reg( 0x10001F, 0x0E000800);	// CLKSRC of EXT_TX_CLK1 = PLL1 (50 MHz)
+
+	/* Port 2: RMII (MAC mode) */
+	sja1105_write_reg( 0x10000D, 0x0A000001);	// Disable IDIV2
+	sja1105_write_reg( 0x100023, 0x04000800);	// CLKSRC of RMII_REF_CLK_2 = TX_CLK_2
+	sja1105_write_reg( 0x100026, 0x0E000800);	// CLKSRC of EXT_TX_CLK2 = PLL1 (50 MHz)
+
+	/* Port 3: RMII (MAC mode) */
+	sja1105_write_reg( 0x10000E, 0x0A000001);	// Disable IDIV3
+	sja1105_write_reg( 0x10002A, 0x06000800);	// CLKSRC of RMII_REF_CLK_3 = TX_CLK_3
+	sja1105_write_reg( 0x10002D, 0x0E000800);	// CLKSRC of EXT_TX_CLK3 = PLL1 (50 MHz)
+
+	/* Port 4: RMII (PHY mode = external REFCLK) */
+	sja1105_write_reg( 0x10000F, 0x0A000001);	// Disable IDIV4
+	sja1105_write_reg( 0x100031, 0x08000800);	// CLKSRC of RMII_REF_CLK_4 = TX_CLK_4
+}
+
+void sja1105_configure_io(void)
+{
+	/* Port 0 and Port 4 RX */
+	/* Enable pull down on CPU Port RX_DV/CRS_DV/RX_CTL and RX_ER and RX_CLK/RXC and RXD2 RXD3 */
+	sja1105_write_reg(0x100801, 0x03020313);
+	sja1105_write_reg(0x100809, 0x03020313);
+
+	/* Port 1 to Port 3 RX */
+	/* Enable pull down on CPU Port ... and RX_CLK/RXC and RXD2 RXD3 */
+	// TODO: What is ...
+	sja1105_write_reg(0x100803, 0x03020213);
+	sja1105_write_reg(0x100805, 0x03020213);
+	sja1105_write_reg(0x100807, 0x03020213);
+
+	/* Port 0 to Port 4 TX */
+	/* Enable pull down on CPU Port TX_ER and TXD2 TXD3 */
+	sja1105_write_reg(0x100800, 0x13121312);
+	sja1105_write_reg(0x100802, 0x13121312);
+	sja1105_write_reg(0x100804, 0x13121312);
+	sja1105_write_reg(0x100806, 0x13121312);
+	sja1105_write_reg(0x100808, 0x13121312);
+}
+
+#if 0
+/*
+ * readout and print the configured IO pads (unused IOs)
+ */
+static void sja1105_read_io(void)
+{
+	uint32_t val;
+
+	val = sja1105_read_reg(0x100801);
+	printf("CFG_PAD_MII0_RX Reg: %08x\n", val);
+	val = sja1105_read_reg(0x100800);
+	printf("CFG_PAD_MII0_TX Reg: %08x\n", val);
+
+	val = sja1105_read_reg(0x100803);
+	printf("CFG_PAD_MII1_RX Reg: %08x\n", val);
+	val = sja1105_read_reg(0x100802);
+	printf("CFG_PAD_MII1_TX Reg: %08x\n", val);
+
+	val = sja1105_read_reg(0x100805);
+	printf("CFG_PAD_MII2_RX Reg: %08x\n", val);
+	val = sja1105_read_reg(0x100804);
+	printf("CFG_PAD_MII2_TX Reg: %08x\n", val);
+
+	val = sja1105_read_reg(0x100807);
+	printf("CFG_PAD_MII3_RX Reg: %08x\n", val);
+	val = sja1105_read_reg(0x100806);
+	printf("CFG_PAD_MII3_TX Reg: %08x\n", val);
+
+	val = sja1105_read_reg(0x100809);
+	printf("CFG_PAD_MII4_RX Reg: %08x\n", val);
+	val = sja1105_read_reg(0x100808);
+	printf("CFG_PAD_MII4_TX Reg: %08x\n", val);
+}
+
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+
+static int do_sjainfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uint32_t p0_mac_stat;
+	uint32_t p0_txf;
+	uint32_t p0_rxf;
+	uint32_t p1_mac_stat;
+	uint32_t p1_txf;
+	uint32_t p1_rxf;
+	uint32_t p2_mac_stat;
+	uint32_t p2_rxf;
+	uint32_t p2_txf;
+	uint32_t p3_mac_stat;
+	uint32_t p3_txf;
+	uint32_t p3_rxf;
+	uint32_t p4_mac_stat;
+	uint32_t p4_rxf;
+	uint32_t p4_txf;
+
+	sja1105_claim_bus();
+
+	p0_mac_stat = sja1105_read_reg(0x00200);
+	p0_rxf = sja1105_read_reg(0x00406);
+	p0_txf = sja1105_read_reg(0x00402);
+
+	p1_mac_stat = sja1105_read_reg(0x00202);
+	p1_rxf = sja1105_read_reg(0x00416);
+	p1_txf = sja1105_read_reg(0x00412);
+
+	p2_mac_stat = sja1105_read_reg(0x00204);
+	p2_rxf = sja1105_read_reg(0x00426);
+	p2_txf = sja1105_read_reg(0x00422);
+
+	p3_mac_stat = sja1105_read_reg(0x00206);
+	p3_rxf = sja1105_read_reg(0x00436);
+	p3_txf = sja1105_read_reg(0x00432);
+
+	p4_mac_stat = sja1105_read_reg(0x00208);
+	p4_rxf = sja1105_read_reg(0x00446);
+	p4_txf = sja1105_read_reg(0x00442);
+
+	sja1105_release_bus();
+
+	printf("Port            MAC Stat Rx  Tx\n");
+	printf("0 (UM)       : %08x %u %u\n", p0_mac_stat, p0_rxf, p0_txf);
+	printf("1 (BroadR-0) : %08x %u %u\n", p1_mac_stat, p1_rxf, p1_txf);
+	printf("2 (BroadR-1) : %08x %u %u\n", p2_mac_stat, p2_rxf, p2_txf);
+	printf("3 (100bTx)   : %08x %u %u\n", p3_mac_stat, p3_rxf, p3_txf);
+	printf("4 (CPU)      : %08x %u %u\n", p4_mac_stat, p4_rxf, p4_txf);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	sjainfo, 1, 1, do_sjainfo,
+	"show eth switch information",
+	""
+);
+
+#endif

board/nm/nmhw21/sja1105.h

@@ -0,0 +1,89 @@
+/*
+ * sja1105.c
+ *
+ * Functions for NXP SJA1105 Ethernet Switch
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SJA1105_H_
+#define _SJA1105_H_
+
+#define SJA_REG_DEVICE_ID	0x000000
+#define SJA_REG_CONFIG_STATUS	0x000001
+
+/**
+ * Initializes the sja1105 driver.
+ *
+ * Must be called before any other function can be used.
+ * Takes and remembers SPI driver for later calls.
+ *
+ * @param spi	SPI driver instance
+ */
+void sja1105_init(struct spi_slave *spi);
+
+/**
+ * Claims bus for subsequent switch accesses.
+ */
+void sja1105_claim_bus(void);
+
+/**
+ * Releases bus.
+ */
+void sja1105_release_bus(void);
+
+/**
+ * Reads switch register.
+ *
+ * (multiple register not possible with this function)
+ *
+ * @param address	register to read (range 0x0 to 0x100BC3)
+ * @returns readback data
+ */
+uint32_t sja1105_read_reg(uint32_t address);
+
+/**
+ * Writes switch register.
+ *
+ * @param address	register to write (range 0x0 to 0x100BC3)
+ * @param data		data to write
+ */
+void sja1105_write_reg(uint32_t address, uint32_t data);
+
+/**
+ * Loads switch firmware.
+ *
+ * This function must be called after the switch has been powered up
+ *
+ * When the device is powered up, it expects to receive an input stream
+ * containing initial setup information over the configuration interface.
+ * The initial configuration data sets the port modes, sets up VLANs
+ * and defines other forwarding and quality-of-service rules.
+ *
+ * This function takes care of loading the configuration according to the
+ * SJA1105 user manual.
+ */
+void sja1105_configure_firmware(void);
+
+/**
+ * Configures the PLL, the CGU and the Auxiliary Configuration Unit.
+ *
+ * Notes: sja1105_configure_firmware() must be called prior to this function.
+ *
+ * Mode and clock description :
+ * - RMII operation on all ports:
+ * - PLL 1 setup for 50Mhz
+ * - Port 0 and 4: RMII (PHY mode = external REFCLK)
+ * - Port 1,2 and 3: RMII (MAC mode)
+ */
+void sja1105_configure_mode_and_clocks(void);
+
+/**
+ * Configures IO pads to a safe state.
+ *
+ * Unused I/Os: Sets pull down to unused pins and set drive strengths
+ */
+void sja1105_configure_io(void);
+
+#endif /* _SJA1105_H_ */

board/nm/nmhw21/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+		board/nm/nmhw21/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/nmhw21/ui.c

@@ -0,0 +1,219 @@
+/*
+ * ui.c
+ *
+ * User Interface access
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+
+#include "ui.h"
+
+/* TODO: Define as masks */
+/* HW V1.0: PCA9539BS (16 Bit) */
+#define UI_V1_TOP_LED_GREEN		6
+#define UI_V1_TOP_LED_RED		7
+#define UI_V1_BOTTOM_LED_GREEN		9
+#define UI_V1_BOTTOM_LED_RED		8
+
+/* HW V2.0: PCA9538ABS (8 Bit) */
+#define UI_V2_ID_0			0
+#define UI_V2_ID_1			1
+#define UI_V2_TOP_LED_GREEN		2
+#define UI_V2_TOP_LED_RED		3
+#define UI_V2_BOTTOM_LED_GREEN		6
+#define UI_V2_BOTTOM_LED_RED		5
+
+
+#define PCA9538_OUT_REG			0x01
+#define PCA9538_CONF_REG		0x03
+
+#define PCA9539_OUT_REG			0x02
+#define PCA9539_CONF_REG		0x06
+
+
+
+
+
+static int ioext_i2c_bus = 0;
+
+/* -1: unitialized, 0: UI not available, 1: UI V1.x, 2: UI V2.x */
+static int hw_version = -1; 
+static int bus_claimed = 0;
+
+static uint8_t out_reg[2];
+
+
+
+static void set_output(uint bit, bool state)
+{
+	if (state) {
+		out_reg[bit/8U] &= ~(1U << (bit % 8U));
+	}
+	else {
+		out_reg[bit/8U] |=  (1U << (bit % 8U));
+	}
+}
+
+static int switch_i2c_bus(int* old_bus)
+{
+	int ret = 0;
+
+        if (old_bus == 0)
+                return -1;
+
+	*old_bus = i2c_get_bus_num();
+	if (*old_bus != ioext_i2c_bus) {
+		ret = i2c_set_bus_num(ioext_i2c_bus);
+	}
+
+	bus_claimed++;
+
+	return ret;
+}
+
+static void revert_i2c_bus(int bus)
+{
+	if (ioext_i2c_bus != bus) {
+		(void)i2c_set_bus_num(bus);
+	}
+
+	bus_claimed--;
+}
+
+static void detect_version(void)
+{
+	int ret;
+	uint8_t temp = 0;
+
+	hw_version = 0;
+
+	/* Try to detect PCA9539 on V1.x HW */ 
+	ret = i2c_read(CONFIG_UI_V1_I2C_ADDR, 0x00, 1, &temp, 1);
+	if (ret == 0) {
+		hw_version = 1;
+	}
+
+	if (hw_version == 0) {
+		/* Try to detect PCA9538 on V2.x HW */ 
+		ret = i2c_read(CONFIG_UI_V2_I2C_ADDR, 0x00, 1, &temp, 1);
+		if (ret == 0) {
+			hw_version = 2;
+		}
+	}
+}
+
+static void init_io(void)
+{
+	switch (hw_version) {
+		case 1: {
+			uint8_t dir[2] = { 0x00, 0x00 };	/* All IOs = Outputs */
+			(void)i2c_write(CONFIG_UI_V1_I2C_ADDR, PCA9539_CONF_REG, 1, dir, 2);
+
+			out_reg[0] = 0xFF;
+			out_reg[1] = 0xFF;
+			break;
+		}
+
+		case 2: {
+			uint8_t dir[1] = { 0x03 };		/* Keep IO 0 & 1 as inputs */
+			(void)i2c_write(CONFIG_UI_V2_I2C_ADDR, PCA9538_CONF_REG, 1, dir, 1);
+
+			out_reg[0] = 0xFF;
+			break;
+		}
+
+		default:
+			break;
+	}
+}
+
+static void v1_set_top_leds(int red, int green)
+{
+	set_output(UI_V1_TOP_LED_RED, red);
+	set_output(UI_V1_TOP_LED_GREEN, green);
+
+	(void)i2c_write(CONFIG_UI_V1_I2C_ADDR, PCA9539_OUT_REG, 1, out_reg, 2);
+}
+
+static void v1_set_bottom_leds(int red, int green)
+{
+	set_output(UI_V1_BOTTOM_LED_RED, red);
+	set_output(UI_V1_BOTTOM_LED_GREEN, green);
+
+	(void)i2c_write(CONFIG_UI_V1_I2C_ADDR, PCA9539_OUT_REG, 1, out_reg, 2);
+}
+
+static void v2_set_top_leds(int red, int green)
+{
+	set_output(UI_V2_TOP_LED_RED, red);
+	set_output(UI_V2_TOP_LED_GREEN, green);
+
+	(void)i2c_write(CONFIG_UI_V2_I2C_ADDR, PCA9538_OUT_REG, 1, out_reg, 1);
+}
+
+static void v2_set_bottom_leds(int red, int green)
+{
+	set_output(UI_V2_BOTTOM_LED_RED, red);
+	set_output(UI_V2_BOTTOM_LED_GREEN, green);
+
+	(void)i2c_write(CONFIG_UI_V2_I2C_ADDR, PCA9538_OUT_REG, 1, out_reg, 1);
+}
+
+
+void ui_init(int i2c_bus)
+{
+	int bus = -1;
+	int claimed;
+
+	ioext_i2c_bus = i2c_bus;
+
+	claimed = switch_i2c_bus(&bus);
+	if (claimed == 0) {
+		detect_version();
+		init_io();
+	}
+	revert_i2c_bus(bus);
+}
+
+int ui_version(void)
+{
+	return hw_version;
+}
+
+void ui_set_top_led(int red, int green)
+{
+	int bus = -1;
+	int claimed;
+
+	claimed = switch_i2c_bus(&bus);
+	if (claimed == 0) {
+		switch (hw_version) {
+			case 1: v1_set_top_leds(red, green); break;
+			case 2: v2_set_top_leds(red, green); break;
+			default: break;
+		}
+		revert_i2c_bus(bus);
+	}
+}
+
+void ui_set_bottom_led(int red, int green)
+{
+	int bus = -1;
+	int claimed;
+
+	claimed = switch_i2c_bus(&bus);
+	if (claimed == 0) {
+		switch (hw_version) {
+			case 1: v1_set_bottom_leds(red, green); break;
+			case 2: v2_set_bottom_leds(red, green); break;
+			default: break;
+		}
+		revert_i2c_bus(bus);
+	}
+}

board/nm/nmhw21/ui.h

@@ -0,0 +1,39 @@
+/*
+ * ui.c
+ *
+ * User Interface access
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef UI_H
+#define UI_H
+
+
+#define CONFIG_UI_I2C_BUS	1
+
+#define CONFIG_UI_V1_I2C_ADDR	0x74
+#define CONFIG_UI_V2_I2C_ADDR	0x70
+
+
+/**
+ * Initializes user interface module.
+ *
+ * @param i2c_bus Number of I2C bus UI is attached to.
+ */
+extern void ui_init(int i2c_bus);
+
+/**
+ * Returns hardware version of UI.
+ *
+ * @return 0: No or unknown UI
+ *         >0: Version (e.g. 1 or 2)
+ */
+extern int ui_version(void);
+
+void ui_set_top_led(int red, int green);
+void ui_set_bottom_led(int red, int green);
+
+#endif /* UI_H */

board/nm/nmhw21/um.c

@@ -0,0 +1,171 @@
+/*
+ * um.c
+ *
+ * User Module Access
+ *
+ * Copyright (C) 2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+
+#include "um.h"
+
+
+static int um_i2c_bus = 0;
+static int bus_claimed = 0;
+
+static int module_present = 0;
+static um_type_t module_type = UM_TYPE_RESERVED;
+static int hw_version = 0;
+static int hw_revision = 0;
+static struct in_addr ipv4_addr;
+static struct in_addr ipv4_mask;
+
+
+static int switch_i2c_bus(int* old_bus)
+{
+	int ret = 0;
+
+        if (old_bus == NULL)
+                return -1;
+
+	*old_bus = i2c_get_bus_num();
+	if (*old_bus != um_i2c_bus) {
+		ret = i2c_set_bus_num(um_i2c_bus);
+	}
+
+	bus_claimed++;
+
+	return ret;
+}
+
+static void revert_i2c_bus(int bus)
+{
+	if (um_i2c_bus != bus) {
+		(void)i2c_set_bus_num(bus);
+	}
+
+	bus_claimed--;
+}
+
+static void get_version(void)
+{
+	int ret;
+	uint8_t reg[1];
+
+	ret = i2c_read(CONFIG_UM_I2C_ADDR, UM_REG_HW_VER, 1, reg, 1);
+	if (ret == 0) {
+		hw_version  = (reg[0] >> 4) & 0x0F;
+		hw_revision = (reg[0] >> 0) & 0x0F;
+	} else {
+		puts("error reading user module version\n");
+	}
+}
+
+
+static void set_inaddr(const uint8_t* data, struct in_addr* in)
+{
+	in->s_addr = htonl(data[0] << 24 | data[1] << 16 | data[2] << 8 | data[3] << 0);	
+}
+
+static void get_network_address(void)
+{
+	int ret;
+	uint8_t data[8];
+
+	ret = i2c_read(CONFIG_UM_I2C_ADDR, UM_REG_IPV4_ADDR, 1, data, 8);
+	if (ret == 0) {
+		set_inaddr(&data[0], &ipv4_addr);
+		set_inaddr(&data[4], &ipv4_mask);
+	} else {
+		puts("error reading user module network configuration\n");
+	}
+}
+
+static void detect(void)
+{
+	int ret;
+	int i;
+	uint8_t reg[2];
+
+	hw_version = 0;
+
+	/* We don't know how fast the UM boots, try for up to 500 msecs */
+	for (i=0; i<500/10; i++) {
+		/* Try to read detect and type register */ 
+		ret = i2c_read(CONFIG_UM_I2C_ADDR, UM_REG_PRESENCE, 1, reg, 2);
+		if (ret == 0) {
+			/* i2c read was successful, now check presence register */
+			if (reg[UM_REG_PRESENCE] == UM_PRESENCE_TOKEN) {
+				module_present = 1;
+
+				module_type = (um_type_t)(reg[UM_REG_TYPE]);
+			}
+			break;
+		}
+
+		udelay(10*1000);	/* 10 ms */
+	}
+}
+
+
+void um_init(int i2c_bus)
+{
+	int bus = -1;
+	int claimed;
+
+	um_i2c_bus = i2c_bus;
+
+	claimed = switch_i2c_bus(&bus);
+	
+	if (claimed == 0) {
+		detect();
+
+		if (module_present) {
+			/* TODO: Check why this delay is required.
+			 * Is the UM software still reading board descriptor? 
+			 */
+			udelay(50*1000);	/* 50 ms delay (tested with 30 ms) */
+
+			get_version();
+			get_network_address();
+		}
+	}
+
+	revert_i2c_bus(bus);
+}
+
+int um_present(void) 
+{
+	return module_present;
+}
+
+const char* um_type_as_str(void) 
+{
+	switch (module_type) {
+		case UM_TYPE_VCUPRO: return "VCU Pro";
+		default: return "<unknown";
+	}
+}
+
+void um_version(uint8_t *version, uint8_t *revision)
+{
+	if (version != NULL)
+		*version = hw_version;
+
+	if (revision != NULL)
+		*revision = hw_revision;
+}
+
+void um_network_address(struct in_addr* ip, struct in_addr* mask)
+{
+	if (ip != NULL)
+		*ip = ipv4_addr;
+
+	if (mask != NULL)
+		*mask = ipv4_mask;
+}

board/nm/nmhw21/um.h

@@ -0,0 +1,76 @@
+/*
+ * um.h
+ *
+ * User Module Access
+ *
+ * Copyright (C) 2019 NetModule AG - http://www.netmodule.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef UM_H
+#define UM_H
+
+#include <net.h>
+
+
+#define CONFIG_UM_I2C_BUS	1
+#define CONFIG_UM_I2C_ADDR	0x40
+
+#define UM_REG_PRESENCE		0x00	/* Presence register, value = 0xC5 */
+#define UM_REG_TYPE		0x01	/* See um_type_t */
+#define UM_REG_HW_VER		0x04	/* Version.Revision, e.g. 0x21 = v2.1 */
+
+#define UM_REG_IPV4_ADDR	0x10	/* IPv4 address in network byte order, 4 bytes */
+#define UM_REG_IPV4_MASK	0x14	/* IPv4 mask in network byte order, 4 bytes */
+
+#define UM_PRESENCE_TOKEN	0xC5
+
+
+/* Known user modules */
+typedef enum {
+	UM_TYPE_RESERVED = 0,
+	UM_TYPE_VCUPRO = 1,
+
+	UM_TYPE_MAX
+} um_type_t;
+
+
+/**
+ * Initializes user user module.
+ *
+ * @param i2c_bus Number of I2C bus module is attached to.
+ */
+void um_init(int i2c_bus);
+
+/**
+ * Returns whether a module has been detected. 
+ *  
+ * @return 1 if module is detected, 0 otherwise.
+ */
+int um_present(void);
+
+/**
+ * Returns name of module.
+ * 
+ * @return Name of module or "<unknown>".
+ */
+const char* um_type_as_str(void);
+
+/**
+ * Returns hardware version of module.
+ * 
+ * @param version Pointer to variable to receive module version (0..15)
+ * @param revision Pointer to variable to receive module revision (0..15)
+ */
+void um_version(uint8_t *version, uint8_t *revision);
+
+/**
+ * Returns user module IPv4 configuration 
+ * 
+ * @param ip Pointer to variable to receive IPv4 address
+ * @param mask Pointer to variable to receive IPv4 mask
+ */
+void um_network_address(struct in_addr* ip, struct in_addr* mask);
+
+#endif /* UM_H */

board/nm/nrhw20/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NRHW20
+
+config SYS_BOARD
+        default "nrhw20"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_nrhw20"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/nrhw20/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o ../common/da9063.o shield.o shield_can.o shield_comio.o fileaccess.o

board/nm/nrhw20/board.h

@@ -0,0 +1,28 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void disable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
+#endif

board/nm/nrhw20/fileaccess.c

@@ -0,0 +1,40 @@
+#include <common.h>
+#include <fs.h>
+
+#define BLOCK_DEVICE "mmc"
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	/* Read at most file size bytes */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}

board/nm/nrhw20/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/nrhw20/mux.c

@@ -0,0 +1,252 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* CPU GPIOs
+	*
+	* (A17) GPIO0_2: RST_GNSS~
+	* (B17) GPIO0_3: GEOFENCE_GNSS
+	* (B16) GPIO0_4: RTK_STAT_GNSS
+	* (A16) GPIO0_5: EXTINT_GNSS
+	* (C15) GPIO0_6: TIMEPULSE
+	* (C18) GPIO0_7: PWM / SHIELD LATCH
+	* (J18) GPIO0_16: RST_PHY~
+	* (K15) GPIO0_17: PMIC FAULT
+	* (U12) GPIO0_27: RST_SHIELD~
+	*
+	* (V13) GPIO1_14: DIG_OUT
+	* (U13) GPIO1_15: DIG_IN
+	* (R14) GPIO1_20: BT_EN
+	* (V15) GPIO1_21: GSM_PWR_EN
+	* (U16) GPIO1_25: RST_GSM
+	* (T16) GPIO1_26: WLAN_EN
+	* (V17) GPIO1_27: WLAN_IRQ
+	*
+	* (J17) GPIO3_4: PCIe_IO.WAKE
+	* (K18) GPIO3_9: PCIe_IO.W_DIS
+	* (L18) GPIO3_10: PCIe_IO.RST
+	* (C12) GPIO3_17: SIM_SEL
+	* (A14) GPIO3_21: RST_HUB~ (USB)
+	*/
+
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},				/* (A17) gpio0[2] */  /* RST_GNSS */
+	{OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},		/* (B17) gpio0[3] */  /* GEOFENCE_GNSS */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},		/* (B16) gpio0[4] */  /* RTK_STAT_GNSS */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},			/* (A16) gpio0[5] */  /* EXTINT_GNSS */
+	{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (C15) gpio0[6] */  /* TIMEPULSE */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (C18) gpio0[7] */  /* IO_SHIELD */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (K15) gpio0[17] */  /* PMIC_FAULT */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},				/* (U12) gpio0[27] */  /* RST_SHIELD~ */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)},				/* (V13) gpio1[14] */  /* DIG_OUT */
+	{OFFSET(gpmc_ad15), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U13) gpio1[15] */  /* DIG_IN */
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},				/* (R14) gpio1[20] */  /* BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},				/* (V15) gpio1[21] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},				/* (U16) gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},				/* (T16) gpio1[26] */  /* WLAN_EN */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V17) gpio1[27] */  /* WLAN_IRQ */
+
+	/* TODO: What about all the unused GPMC pins ? */
+
+	/* Bank 2 */
+#if 0
+	/* TODO: What is this meant for? */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (R4) gpio2[9] */  /* SYSBOOT_3 */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (T1) gpio2[10] */  /* SYSBOOT_4 */
+
+	/* TODO: Check other unued pins from sysboot block */
+	/* Ensure PU/PD does not work against external signal */
+	/*
+	 * SYSBOOT 0,1,5,12,13 = Low
+	 * SYSBOOT 2 = High
+	 */
+#endif
+
+	/* Bank 3 */
+	{OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (H16) gpio3[0] */  /* BUTTON */
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (J17) gpio3[4] */  /* PCIe_IO.WAKE */
+	{OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)},				/* (K18) gpio3[9] */  /* PCIe_IO.W_DIS */
+	{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)},				/* (L18) gpio3[10] */  /* PCIe_IO.RST */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (C12) gpio3[17] */  /* SIM_SEL */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN)},				/* (A14) gpio3[21] */  /* RST_HUB~ */
+	{-1}
+};
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1}
+};
+
+/* I2C2 System */
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D17) I2C2_SCL */
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D18) I2C2_SDA */
+	{-1},
+};
+
+/* RMII1: Ethernet Switch */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for Switch) */
+	{-1}
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1}
+};
+
+/* UART0: RS232/RS485 shield mode */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* UART0: Shield I/F (UART, CAN) */
+/* Leave UART0 unconfigured because we want to configure it as needed by Linux (can/spi/uart/etc) */
+/* Mode 7 = GPIO */
+static struct module_pin_mux uart0_disabled_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E15) GPIO1_10 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) GPIO1_11 */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E18) GPIO1_8 */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E17) GPIO1_9 */
+	{-1},
+};
+
+/* UART1: User (Debug/Console) */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D15) uart1_txd */
+	{-1},
+};
+
+/* UART3: GNSS */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (L17) UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (L16) UART3_TXD */
+	{-1}
+};
+
+/* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1}
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1}
+};
+
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c2_pin_mux);
+
+	configure_module_pin_mux(uart3_pin_mux);
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void disable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}

board/nm/nrhw20/shield.c

@@ -0,0 +1,74 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define MAX_SHIELDS 16
+
+static struct shield_t *shields[MAX_SHIELDS];
+static int shield_count = 0;
+
+/* Perhaps this function shouldn't leave in shields.c? */
+int shield_gpio_request_as_input(unsigned int gpio, const char *label)
+{
+	int ret;
+
+ 	ret = gpio_request(gpio, label);
+	if ((ret < 0)) {
+		printf("Could not request shield slot %s gpio\n", label);
+		return -1;
+	}
+
+	ret = gpio_direction_input(gpio);
+	if ((ret < 0)) {
+		printf("Could not configure shield slot %s gpio as input\n", label);
+		return -1;
+	}
+
+	return 0;
+}
+
+void shield_register(struct shield_t *shield)
+{
+	if (shield_count >= MAX_SHIELDS) {
+		printf("Max shield count reached (%d), please increment MAX_SHIELDS\n", MAX_SHIELDS);
+		return;
+	}
+	shields[shield_count++] = shield;
+}
+
+int shield_set_mode(const char* shield_type, int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < shield_count; i++) {
+		if (strcmp(shield_type, shields[i]->name) == 0) {
+			return shields[i]->setmode(argv, argc);
+		}
+	}
+	printf("## Error: No %s shield installed\n", shield_type);
+	/* Do not return error, to not show usage (request by rs) */
+	return 0;
+}
+
+static int do_shieldmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		return -1;
+	}
+
+	return shield_set_mode(argv[1], argc - 2, &argv[2]);
+}
+
+U_BOOT_CMD(
+	shield,	6,	1,	do_shieldmode,
+	"Set the shield mode",
+	"dualcan termination [on|off] [on|off]\n"
+	"shield dualcan-passive\n"
+	"shield comio mode [rs232|rs485] termination [on|off]\n"
+);
+

board/nm/nrhw20/shield.h

@@ -0,0 +1,26 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/shield.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Wed 31 May 2017 02:56:16 PM CEST \n
+ * 	Last Update:	Wed 31 May 2017 02:56:16 PM CEST
+ */
+#ifndef SHIELD_H
+#define SHIELD_H
+
+#define SHIELD_COM_IO		0
+#define SHIELD_DUALCAN		1
+#define SHIELD_CAN_GNSS		2
+#define SHIELD_DUALCAN_PASSIVE	3
+
+struct shield_t{
+    char name[64];
+    int (*setmode)(char * const argv[], int argc);
+};
+
+int shield_setmode(int mode);
+void shield_register(struct shield_t *shield);
+
+int shield_gpio_request_as_input(unsigned int gpio, const char *label);
+
+#endif // SHIELD_H

board/nm/nrhw20/shield_can.c

@@ -0,0 +1,214 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define CAN_PORTS			2
+
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LATCH		GPIO_TO_PIN(0, 7)
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 10)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 8)
+
+
+static int shield_slot_initialized = 0;
+
+
+static struct module_pin_mux can_shield_netbird_pin_mux_config[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E18) gpio1_8 */ /* Mode 0 */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E15) gpio1_10 */ /* Mode 1 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* Latch EN */
+	{-1},
+};
+
+static struct module_pin_mux can_shield_netbird_pin_mux_final[] = {
+	{OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E16) dcan0_rx */
+	{OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E15) dcan0_tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E17) dcan1_rx */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E18) dcan1_tx */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LATCH, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type dualcan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Configure shield pin muxing for configuration\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_config);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to high\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LATCH, 1);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to low\n");
+	gpio_set_value(NETBIRD_GPIO_LATCH, 0);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set final can shield muxing\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_final);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	/* TODO: Double check */
+	return (!terminations[0] << 0) | (!terminations[1] << 1);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 3) {
+		debug("Too few arguments for dualcan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+static int no_options(char * const argv[], int argc)
+{
+	if (argc != 0) {
+		debug("Too many arguments\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+
+static struct shield_t can_shield = {
+	"dualcan", set_shieldmode
+};
+
+void can_shield_init(void)
+{
+	shield_register(&can_shield);
+}
+
+static struct shield_t can_shield_passive = {
+	"dualcan-passive", no_options
+};
+
+void can_shield_passive_init(void)
+{
+	shield_register(&can_shield_passive);
+}

board/nm/nrhw20/shield_can.h

@@ -0,0 +1,10 @@
+#ifndef SHIELD_CAN_H
+#define SHIELD_CAN_H
+
+int shield_can_init(void);
+int shield_can_setmode(int mode);
+
+void can_shield_init(void);
+void can_shield_passive_init(void);
+
+#endif // SHIELD_CAN_H

board/nm/nrhw20/shield_comio.c

@@ -0,0 +1,252 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+/* TODO: Double Check */
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LOAD		GPIO_TO_PIN(1, 9)
+/* TODO: Who configures UART0_RTSn, GPIO1_9 ? */
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 11)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 10)
+
+static int shield_slot_initialized = 0;
+
+
+/* TODO: Naming -> config, final */
+static struct module_pin_mux shield_gpio_netbird_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)},			/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured (GPIO) because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Extension slot init\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LOAD, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug ("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type comio\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Enable gpio pull-ups\n");
+	configure_module_pin_mux(shield_gpio_netbird_pin_mux);
+
+	debug("Set load to low\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LOAD, 0);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set load to high\n");
+	gpio_set_value(NETBIRD_GPIO_LOAD, 1);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Disable pullups on shield gpios\n");
+	configure_module_pin_mux(shield_gpio_safe_netbird_pin_mux);
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set gpio load as input again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_LOAD);
+	if (ret < 0) {
+		puts("Can not configure shield slot load as input");
+		return -1;
+	}
+
+	return 0;
+}
+
+enum mode_nr {
+	RS232,
+	RS485,
+	UNKNOWN
+};
+
+struct mode {
+	enum mode_nr nr;
+	const char* name;
+	int argc;
+};
+
+struct mode modes[] = {
+	{ RS232, "rs232", 0 },
+	{ RS485, "rs485", 2 }
+};
+
+static const struct mode *get_mode(const char *mode)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		if (strcmp(modes[i].name, mode) == 0) {
+			return &modes[i];
+		}
+	}
+	return NULL;
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int termination = 0;
+	int rs232 = 0;
+	const struct mode *selected_mode;
+
+	assert(argc >= 2);
+
+	if (strcmp ("mode", argv[0])) {
+		debug("Invalid arguments (see help)\n");
+		return -1;
+	}
+
+	selected_mode = get_mode(argv[1]);
+	if (selected_mode == NULL) {
+		debug("Mode %s not supported\n", argv[1]);
+		return -1;
+	}
+
+	debug ("Mode %s, index %d, argc %d\n", selected_mode->name,
+			selected_mode->nr, selected_mode->argc);
+
+	if (selected_mode->argc != argc - 2) {
+		debug("Invalid argument count for mode %s (should %d is %d)\n",
+				argv[1],  selected_mode->argc, argc - 2);
+		return -1;
+	}
+
+	if (selected_mode->nr == RS485) {
+		if (strcmp("termination", argv[2])) {
+			debug("Invalid arguments, do not configure termination\n");
+			return -1;
+		}
+
+		termination = get_termination(argv[3]);
+		if (termination < 0) {
+			debug("Invalid termination %s\n", argv[3]);
+			return -1;
+		}
+	}
+	else {
+		rs232 = 1;
+	}
+
+	/* Termination is inverse */
+	return (rs232 << 0) | ((!termination) << 1);
+}
+
+int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc < 2) {
+		debug("Too few arguments for comio\n");
+		return -1;
+	}
+
+	/* -1 will make configure_shieldmode to faile and is okay therefore */
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+/* TODO: Static ? */
+struct shield_t comio_shield = {
+	"comio", set_shieldmode
+};
+
+void comio_shield_init(void)
+{
+	shield_register(&comio_shield);
+}

board/nm/nrhw20/shield_comio.h

@@ -0,0 +1,6 @@
+#ifndef SHIELD_COMIO_H
+#define SHIELD_COMIO_H
+
+void comio_shield_init(void);
+
+#endif // SHIELD_COMIO_H

board/nm/nrhw20/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+                board/nm/nrhw20/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

board/nm/nrhw24/Kconfig

@@ -0,0 +1,26 @@
+if TARGET_AM335X_NRHW24
+
+config SYS_BOARD
+        default "nrhw24"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_nrhw24"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+

board/nm/nrhw24/Makefile

@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o ../common/da9063.o shield.o shield_can.o shield_comio.o fileaccess.o

board/nm/nrhw24/board.h

@@ -0,0 +1,28 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void disable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+
+#endif

board/nm/nrhw24/fileaccess.c

@@ -0,0 +1,40 @@
+#include <common.h>
+#include <fs.h>
+
+#define BLOCK_DEVICE "mmc"
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	/* Read at most file size bytes */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}

board/nm/nrhw24/fileaccess.h

@@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H

board/nm/nrhw24/mux.c

@@ -0,0 +1,233 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018-2019 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* CPU GPIOs
+	*
+	* (A17) GPIO0_2: RST_GNSS~
+	* (A16) GPIO0_5: EXTINT_GNSS
+	* (C15) GPIO0_6: TIMEPULSE
+	* (C18) GPIO0_7: PWM / SHIELD LATCH
+	* (J18) GPIO0_16: RST_PHY~
+	* (U12) GPIO0_27: RST_SHIELD~
+	*
+	* (R14) GPIO1_20: BT_EN
+	* (V15) GPIO1_21: GSM_PWR_EN
+	* (U16) GPIO1_25: RST_GSM
+	* (T16) GPIO1_26: WLAN_EN
+	* (V17) GPIO1_27: WLAN_IRQ
+	*
+	* (C12) GPIO3_17: SIM_SEL
+	*/
+
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},				/* (A17) gpio0[2] */  /* RST_GNSS */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},			/* (A16) gpio0[5] */  /* EXTINT_GNSS */
+	{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (C15) gpio0[6] */  /* TIMEPULSE */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (C18) gpio0[7] */  /* IO_SHIELD */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},				/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},				/* (U12) gpio0[27] */  /* RST_SHIELD~ */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},				/* (R14) gpio1[20] */  /* BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},				/* (V15) gpio1[21] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},				/* (U16) gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},				/* (T16) gpio1[26] */  /* WLAN_EN */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (V17) gpio1[27] */  /* WLAN_IRQ */
+
+	/* TODO: What about all the unused GPMC pins ? */
+
+	/* Bank 2 */
+#if 0
+	/* TODO: What is this meant for? */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (R4) gpio2[9] */  /* SYSBOOT_3 */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (T1) gpio2[10] */  /* SYSBOOT_4 */
+
+	/* TODO: Check other unued pins from sysboot block */
+	/* Ensure PU/PD does not work against external signal */
+	/*
+	 * SYSBOOT 0,1,5,12,13 = Low
+	 * SYSBOOT 2 = High
+	 */
+#endif
+
+	/* Bank 3 */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (C12) gpio3[17] */  /* SIM_SEL */
+	{-1}
+};
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1}
+};
+
+/* I2C2 System */
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D17) I2C2_SCL */
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D18) I2C2_SDA */
+	{-1},
+};
+
+/* RMII1: Ethernet */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for PHY) */
+	{-1}
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G17) MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G18) MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G16) MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (G15) MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F18) MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (F17) MMC0_DAT3 */
+	{-1}
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U9) MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V9) MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U7) MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V7) MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R8) MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T8) MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U8) MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V8) MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (R9) MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (T9) MMC1_DAT7 */
+	{-1}
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1}
+};
+
+/* UART0: RS232/RS485 shield mode */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* UART0: Shield I/F (UART, CAN) */
+/* Leave UART0 unconfigured because we want to configure it as needed by Linux (can/spi/uart/etc) */
+/* Mode 7 = GPIO */
+static struct module_pin_mux uart0_disabled_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E15) GPIO1_10 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) GPIO1_11 */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E18) GPIO1_8 */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E17) GPIO1_9 */
+	{-1},
+};
+
+/* UART1: User (Debug/Console) */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D15) uart1_txd */
+	{-1},
+};
+
+/* UART3: GNSS */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (L17) UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (L16) UART3_TXD */
+	{-1}
+};
+
+/* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1}
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1}
+};
+
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c2_pin_mux);
+
+	configure_module_pin_mux(uart3_pin_mux);
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void disable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}

board/nm/nrhw24/shield.c

@@ -0,0 +1,74 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define MAX_SHIELDS 16
+
+static struct shield_t *shields[MAX_SHIELDS];
+static int shield_count = 0;
+
+/* Perhaps this function shouldn't leave in shields.c? */
+int shield_gpio_request_as_input(unsigned int gpio, const char *label)
+{
+	int ret;
+
+ 	ret = gpio_request(gpio, label);
+	if ((ret < 0)) {
+		printf("Could not request shield slot %s gpio\n", label);
+		return -1;
+	}
+
+	ret = gpio_direction_input(gpio);
+	if ((ret < 0)) {
+		printf("Could not configure shield slot %s gpio as input\n", label);
+		return -1;
+	}
+
+	return 0;
+}
+
+void shield_register(struct shield_t *shield)
+{
+	if (shield_count >= MAX_SHIELDS) {
+		printf("Max shield count reached (%d), please increment MAX_SHIELDS\n", MAX_SHIELDS);
+		return;
+	}
+	shields[shield_count++] = shield;
+}
+
+int shield_set_mode(const char* shield_type, int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < shield_count; i++) {
+		if (strcmp(shield_type, shields[i]->name) == 0) {
+			return shields[i]->setmode(argv, argc);
+		}
+	}
+	printf("## Error: No %s shield installed\n", shield_type);
+	/* Do not return error, to not show usage (request by rs) */
+	return 0;
+}
+
+static int do_shieldmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		return -1;
+	}
+
+	return shield_set_mode(argv[1], argc - 2, &argv[2]);
+}
+
+U_BOOT_CMD(
+	shield,	6,	1,	do_shieldmode,
+	"Set the shield mode",
+	"dualcan termination [on|off] [on|off]\n"
+	"shield dualcan-passive\n"
+	"shield comio mode [rs232|rs485] termination [on|off]\n"
+);
+

board/nm/nrhw24/shield.h

@@ -0,0 +1,26 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/shield.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Wed 31 May 2017 02:56:16 PM CEST \n
+ * 	Last Update:	Wed 31 May 2017 02:56:16 PM CEST
+ */
+#ifndef SHIELD_H
+#define SHIELD_H
+
+#define SHIELD_COM_IO		0
+#define SHIELD_DUALCAN		1
+#define SHIELD_CAN_GNSS		2
+#define SHIELD_DUALCAN_PASSIVE	3
+
+struct shield_t{
+    char name[64];
+    int (*setmode)(char * const argv[], int argc);
+};
+
+int shield_setmode(int mode);
+void shield_register(struct shield_t *shield);
+
+int shield_gpio_request_as_input(unsigned int gpio, const char *label);
+
+#endif // SHIELD_H

board/nm/nrhw24/shield_can.c

@@ -0,0 +1,214 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define CAN_PORTS			2
+
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LATCH		GPIO_TO_PIN(0, 7)
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 10)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 8)
+
+
+static int shield_slot_initialized = 0;
+
+
+static struct module_pin_mux can_shield_netbird_pin_mux_config[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E18) gpio1_8 */ /* Mode 0 */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E15) gpio1_10 */ /* Mode 1 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* Latch EN */
+	{-1},
+};
+
+static struct module_pin_mux can_shield_netbird_pin_mux_final[] = {
+	{OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E16) dcan0_rx */
+	{OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E15) dcan0_tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E17) dcan1_rx */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E18) dcan1_tx */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LATCH, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type dualcan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Configure shield pin muxing for configuration\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_config);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to high\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LATCH, 1);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to low\n");
+	gpio_set_value(NETBIRD_GPIO_LATCH, 0);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set final can shield muxing\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_final);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	/* TODO: Double check */
+	return (!terminations[0] << 0) | (!terminations[1] << 1);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 3) {
+		debug("Too few arguments for dualcan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+static int no_options(char * const argv[], int argc)
+{
+	if (argc != 0) {
+		debug("Too many arguments\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+
+static struct shield_t can_shield = {
+	"dualcan", set_shieldmode
+};
+
+void can_shield_init(void)
+{
+	shield_register(&can_shield);
+}
+
+static struct shield_t can_shield_passive = {
+	"dualcan-passive", no_options
+};
+
+void can_shield_passive_init(void)
+{
+	shield_register(&can_shield_passive);
+}

board/nm/nrhw24/shield_can.h

@@ -0,0 +1,10 @@
+#ifndef SHIELD_CAN_H
+#define SHIELD_CAN_H
+
+int shield_can_init(void);
+int shield_can_setmode(int mode);
+
+void can_shield_init(void);
+void can_shield_passive_init(void);
+
+#endif // SHIELD_CAN_H

board/nm/nrhw24/shield_comio.c

@@ -0,0 +1,252 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+/* TODO: Double Check */
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LOAD		GPIO_TO_PIN(1, 9)
+/* TODO: Who configures UART0_RTSn, GPIO1_9 ? */
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 11)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 10)
+
+static int shield_slot_initialized = 0;
+
+
+/* TODO: Naming -> config, final */
+static struct module_pin_mux shield_gpio_netbird_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)},			/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured (GPIO) because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Extension slot init\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LOAD, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug ("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type comio\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Enable gpio pull-ups\n");
+	configure_module_pin_mux(shield_gpio_netbird_pin_mux);
+
+	debug("Set load to low\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LOAD, 0);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set load to high\n");
+	gpio_set_value(NETBIRD_GPIO_LOAD, 1);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Disable pullups on shield gpios\n");
+	configure_module_pin_mux(shield_gpio_safe_netbird_pin_mux);
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set gpio load as input again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_LOAD);
+	if (ret < 0) {
+		puts("Can not configure shield slot load as input");
+		return -1;
+	}
+
+	return 0;
+}
+
+enum mode_nr {
+	RS232,
+	RS485,
+	UNKNOWN
+};
+
+struct mode {
+	enum mode_nr nr;
+	const char* name;
+	int argc;
+};
+
+struct mode modes[] = {
+	{ RS232, "rs232", 0 },
+	{ RS485, "rs485", 2 }
+};
+
+static const struct mode *get_mode(const char *mode)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		if (strcmp(modes[i].name, mode) == 0) {
+			return &modes[i];
+		}
+	}
+	return NULL;
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int termination = 0;
+	int rs232 = 0;
+	const struct mode *selected_mode;
+
+	assert(argc >= 2);
+
+	if (strcmp ("mode", argv[0])) {
+		debug("Invalid arguments (see help)\n");
+		return -1;
+	}
+
+	selected_mode = get_mode(argv[1]);
+	if (selected_mode == NULL) {
+		debug("Mode %s not supported\n", argv[1]);
+		return -1;
+	}
+
+	debug ("Mode %s, index %d, argc %d\n", selected_mode->name,
+			selected_mode->nr, selected_mode->argc);
+
+	if (selected_mode->argc != argc - 2) {
+		debug("Invalid argument count for mode %s (should %d is %d)\n",
+				argv[1],  selected_mode->argc, argc - 2);
+		return -1;
+	}
+
+	if (selected_mode->nr == RS485) {
+		if (strcmp("termination", argv[2])) {
+			debug("Invalid arguments, do not configure termination\n");
+			return -1;
+		}
+
+		termination = get_termination(argv[3]);
+		if (termination < 0) {
+			debug("Invalid termination %s\n", argv[3]);
+			return -1;
+		}
+	}
+	else {
+		rs232 = 1;
+	}
+
+	/* Termination is inverse */
+	return (rs232 << 0) | ((!termination) << 1);
+}
+
+int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc < 2) {
+		debug("Too few arguments for comio\n");
+		return -1;
+	}
+
+	/* -1 will make configure_shieldmode to faile and is okay therefore */
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+/* TODO: Static ? */
+struct shield_t comio_shield = {
+	"comio", set_shieldmode
+};
+
+void comio_shield_init(void)
+{
+	shield_register(&comio_shield);
+}

board/nm/nrhw24/shield_comio.h

@@ -0,0 +1,6 @@
+#ifndef SHIELD_COMIO_H
+#define SHIELD_COMIO_H
+
+void comio_shield_init(void);
+
+#endif // SHIELD_COMIO_H

board/nm/nrhw24/u-boot.lds

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+                board/nm/nrhw24/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}

cmd/mdio.c

@@ -24,6 +24,29 @@ static uint last_devad_hi;
 static uint last_reg_lo;
 static uint last_reg_hi;
 
+
+static int mdio_wait_for_link(struct phy_device *phydev, struct mii_dev *bus)
+{
+	int link;
+	int res;
+
+	printf("waiting for link up on %s\n", bus->name);
+	
+	phy_startup(phydev);
+
+	link = phydev->link;
+	if (link) {
+		printf("link up\n");
+		res = 0;
+	}
+	else {
+		printf("no link\n");
+		res = 1;
+	}
+
+	return res;
+}
+
 static int extract_range(char *input, int *plo, int *phi)
 {
 	char *end;
@@ -191,6 +214,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	struct mii_dev *bus;
 	struct phy_device *phydev = NULL;
 	int extended = 0;
+	int res = 0;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
@@ -213,7 +237,14 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (flag & CMD_FLAG_REPEAT)
 		op[0] = last_op[0];
 
-	if (strlen(argv[1]) > 1) {
+	if (strcmp(argv[1], "up") == 0)	{
+		if (argc >= 3) {
+			phydev = mdio_phydev_for_ethname(argv[2]);
+		} else {
+			return CMD_RET_USAGE;
+		}
+	}
+	else if (strlen(argv[1]) > 1) {
 		op[1] = argv[1][1];
 		if (op[1] == 'x') {
 			phydev = mdio_phydev_for_ethname(argv[2]);
@@ -274,6 +305,10 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi,
 				 reglo, reghi, extended);
 		break;
+	
+	case 'u':
+		res = mdio_wait_for_link(phydev, bus);
+		break;
 	}
 
 	/*
@@ -288,7 +323,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	last_reg_hi  = reghi;
 	last_data    = data;
 
-	return 0;
+	return res;
 }
 
 /***************************************************/
@@ -305,6 +340,7 @@ U_BOOT_CMD(
 		"read PHY's extended register at <devad>.<reg>\n"
 	"mdio wx <phydev> [<devad>.]<reg> <data> - "
 		"write PHY's extended register at <devad>.<reg>\n"
+	"mdio up <phydev> - wait for PHY link to become ready (up)\n"
 	"<phydev> may be:\n"
 	"   <busname>  <addr>\n"
 	"   <addr>\n"

cmd/pxe.c

@@ -620,7 +620,7 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 	char initrd_str[22];
 	char mac_str[29] = "";
 	char ip_str[68] = "";
-	int bootm_argc = 3;
+	int bootm_argc = 2;
 	int len = 0;
 	ulong kernel_addr;
 	void *buf;
@@ -652,8 +652,6 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 		strcpy(bootm_argv[2], getenv("ramdisk_addr_r"));
 		strcat(bootm_argv[2], ":");
 		strcat(bootm_argv[2], getenv("filesize"));
-	} else {
-		bootm_argv[2] = "-";
 	}
 
 	if (get_relfile_envaddr(cmdtp, label->kernel, "kernel_addr_r") < 0) {
@@ -785,8 +783,11 @@ static int label_boot(cmd_tbl_t *cmdtp, struct pxe_label *label)
 	if (!bootm_argv[3])
 		bootm_argv[3] = getenv("fdt_addr");
 
-	if (bootm_argv[3])
+	if (bootm_argv[3]) {
+		if (!bootm_argv[2])
+			bootm_argv[2] = "-";
 		bootm_argc = 4;
+	}
 
 	kernel_addr = genimg_get_kernel_addr(bootm_argv[1]);
 	buf = map_sysmem(kernel_addr, 0);

common/board_f.c

@@ -888,8 +888,10 @@ static init_fnc_t init_sequence_f[] = {
 	init_timebase,
 #endif
 	init_baud_rate,		/* initialze baudrate settings */
+#if !defined(CONFIG_PRE_CONSOLE_BUFFER)
 	serial_init,		/* serial communications setup */
 	console_init_f,		/* stage 1 init of console */
+#endif
 #ifdef CONFIG_SANDBOX
 	sandbox_early_getopt_check,
 #endif

common/console.c

@@ -414,7 +414,7 @@ int tstc(void)
 #define PRE_CONSOLE_FLUSHPOINT2_EVERYTHING_BUT_SERIAL	1
 
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
-#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)CONFIG_PRE_CON_BUF_SZ)
+#define CIRC_BUF_IDX(idx) ((idx) % (unsigned long)(CONFIG_PRE_CON_BUF_SZ))
 
 static void pre_console_putc(const char c)
 {

common/main.c

@@ -13,6 +13,22 @@
 #include <console.h>
 #include <version.h>
 
+#ifdef CONFIG_NM_LOGIN
+#include <fs.h>
+#include <u-boot/md5.h>
+#include <malloc.h>
+#include <crypt.h>
+
+/* Set defaults for passwd file location */
+#ifndef CONFIG_NM_LOGIN_PART
+#define CONFIG_NM_LOGIN_PART	"1:3"
+#endif
+#ifndef CONFIG_NM_LOGIN_PASSWD
+#define CONFIG_NM_LOGIN_PASSWD	"/root/boot/bootpass"
+#endif
+
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -20,6 +36,112 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 __weak void show_boot_progress(int val) {}
 
+
+#ifdef CONFIG_NM_LOGIN
+/****************************************************************************
+ *  check if ubootpwd exists in data partition and perform a login,
+ *  otherwise continue booting
+ */
+int login (void)
+{
+	#define MAX_TRIES_ENTER 4096
+	#define PASSWORD_LEN 256
+
+	char stored_pw_hash[PASSWORD_LEN];
+	char password[PASSWORD_LEN];
+	int res, i, tries;
+	int legacy_md5 = 0;
+	loff_t actread;
+	char c;
+
+	puts("\nautoboot has been stopped, press 'e' to enter: ");
+
+	for (i=0; i<=MAX_TRIES_ENTER; i++) {
+		c = getc();
+		if (c == 'e' || c == '\n') {
+			puts("e");
+			break;
+		}
+
+		/* Enter condition not given -> restart */
+		if (i == MAX_TRIES_ENTER) 
+			return 0;
+	}
+	puts("\n");
+
+	/* Try to get password hash file */
+	memset(stored_pw_hash, 0x0, sizeof(stored_pw_hash));
+	if (fs_set_blk_dev("mmc", CONFIG_NM_LOGIN_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return 1;
+	}
+
+	res = fs_read(CONFIG_NM_LOGIN_PASSWD, (ulong)stored_pw_hash, 0, sizeof(stored_pw_hash), &actread);
+	if ((res != 0) || (actread <= 0)) {
+		/* no file or hash found -> allow login w/o password */
+		puts("Login succeeded\n\n");
+		return 1;
+	} else if (actread == 16) {
+		legacy_md5 = 1;
+	}
+
+	for (tries = 1; ; tries++) {
+		puts("\nEnter password: ");
+
+		/* TODO: no backspace ? */
+		/* TODO: rename buf to something more useful */
+		/* TODO: print a dot or blind? */
+		password[0] = 0;
+		for (i=0; i<PASSWORD_LEN; i++) {
+			password[i] = getc();
+			if (password[i] == '\r' || password[i] == '\n') {
+				password[i] = 0;
+				break;
+			}
+		}
+		password[PASSWORD_LEN-1] = 0;
+
+		if (strlen(password) > 0) {
+			puts("\n");
+			if (legacy_md5) {
+				/* MD5 - legacy */
+				char entered[32];	/* TODO: Why 32, MD5 algo uses only 16 bytes */
+
+				md5((unsigned char *)password, strlen(password), (unsigned char *)entered);
+				if (memcmp(stored_pw_hash, entered, 16) == 0) {
+					break;
+				}
+			}
+			else {
+				/* SHA256 */
+				char *cp = sha_crypt(password, stored_pw_hash);	/* TODO: Salt = PW? */
+				res = memcmp(cp, stored_pw_hash, actread);
+				free(cp);
+				if (res == 0)
+					break;
+			}
+
+			/* TODO: exponentional delay */
+			puts("Login incorrect\n");
+			if (tries == 3) {
+				return 0;
+			}
+		}
+
+		/* TODO: remove password from memory !!!!! */
+		memset(password, 0, sizeof(password));
+	}
+
+	/* succeeded */
+	puts("Login succeeded\n\n");
+
+	return 1;
+}
+
+#endif /* CONIFG_NM_LOGIN */
+
+/****************************************************************************/
+
 static void run_preboot_environment_command(void)
 {
 #ifdef CONFIG_PREBOOT
@@ -65,6 +187,13 @@ void main_loop(void)
 
 	autoboot_command(s);
 
+#ifdef CONFIG_NM_LOGIN
+	if (!login()) {
+		puts ("Login failed, resetting...\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+#endif
+
 	cli_loop();
 	panic("No CLI available");
 }

common/spl/spl.c

@@ -19,6 +19,10 @@
 #include <dm/root.h>
 #include <linux/compiler.h>
 
+#ifdef CONFIG_NRSW_BUILD
+#include <spl_version_autogenerated.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_UBOOT_START
@@ -453,7 +457,12 @@ void preloader_console_init(void)
 
 	gd->have_console = 1;
 
-	puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
+#ifdef CONFIG_NRSW_BUILD
+	puts("\n" SPL_VERSION "\n");
+#else
+	puts("\n");
+#endif
+	puts("U-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
 			U_BOOT_TIME ")\n");
 #ifdef CONFIG_SPL_DISPLAY_PRINT
 	spl_display_print();

common/spl/spl_mmc.c

@@ -15,20 +15,166 @@
 #include <errno.h>
 #include <mmc.h>
 #include <image.h>
+#include <crc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+
+#define UBOOT_MIN_SIZE_BYTES	(128*1024)
+#define UBOOT_MAX_SIZE_BYTES	(2500*1024)
+
+#if defined(CONFIG_NM_BOOTLOADER_FORMAT)
+
+static int image_nm_header_ok(const struct nm_header *header)
+{
+	u32 start_tag = __be32_to_cpu(header->nm_start_tag);
+	u32 length = __be32_to_cpu(header->nm_length);
+
+	if ((start_tag == 0x424c5354) &&
+	    (length >= UBOOT_MIN_SIZE_BYTES) && (length <= UBOOT_MAX_SIZE_BYTES))
+	{
+		return 0;
+	}
+	else {
+		return -EFAULT;
+	}
+}
+
+static int mmc_load_netmodule(struct mmc *mmc, ulong sector,
+			      const struct nm_header *header)
+{
+	u32 nm_header_size = sizeof(struct nm_header) -sizeof(struct image_header);
+	const struct image_header *im_header;
+	const __be32* end_tag_position;
+	u32 image_size_sectors;
+	unsigned long count; 
+	u32 end_tag;
+	int ret;
+
+	im_header = &(header->header);
+
+	/* decode header and fill out spl_image structure */
+	ret = spl_parse_image_header(im_header);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * convert size to sectors - round up,
+	 * add 256 bytes for NetModule header, 4 bytes for NetModule trailer 
+	 */
+	image_size_sectors = (spl_image.size + nm_header_size + sizeof(u32) + 
+			     mmc->read_bl_len - 1) /
+			     mmc->read_bl_len;
+
+	/*
+	 * Read the header too to avoid extra memcpy,
+	 * compensate the load address for the NetModule header 
+	 */
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
+			  (void *)(ulong)spl_image.load_addr - nm_header_size);
+	debug("read %x sectors to %x\n", image_size_sectors,
+	      spl_image.load_addr);
+
+	if (count != image_size_sectors) {
+		puts(", read error");
+		return -EIO;
+	}
+
+	/* Check NetModule end tag to be sure image is completely written */
+	end_tag_position =  (const __be32*)(spl_image.load_addr + spl_image.size);
+	end_tag = __be32_to_cpu(*end_tag_position);
+	if (end_tag != 0x424c454e) {
+		puts(", end marker fail");
+		return -EFAULT;
+	}
+
+	puts(", end marker ok");
+
+	return 0;
+}
+
+static int mmc_load_image_raw_sector_netmodule(struct mmc *mmc, unsigned long sector)
+{
+	unsigned long count;
+	struct nm_header *header;
+	int ret = 0;
+
+	printf("Checking NM U-Boot at sector 0x%lx: ", sector);
+
+	header = (struct nm_header *)(CONFIG_SYS_TEXT_BASE -
+					 sizeof(struct nm_header));
+
+	/* read image header to find the image size and load address */
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
+	debug("hdr read sector %lx, count=%lu\n", sector, count);
+	if (count == 0) {
+		ret = -EIO;
+		goto end;
+	}
+
+	if (image_nm_header_ok(header)) {
+		puts("hdr fail");
+		ret = -EFAULT;
+		goto end;
+	}
+
+	puts("hdr ok");
+
+	ret = mmc_load_netmodule(mmc, sector, header);
+
+end:
+	if (ret) {
+		puts(" -> skipping\n");
+		return -1;
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+#endif /* CONFIG_NM_BOOTLOADER_FORMAT) */
+
 static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 			   struct image_header *header)
 {
+	u32 header_size = sizeof(struct image_header);
 	u32 image_size_sectors;
+	u32 image_size_bytes;
+	u32 data_crc;
+	u32 data_crc_memory;
 	unsigned long count;
 	int ret;
 
+	/*
+	 * Note: spl_parse_image_header() always returns 0 
+	 * Own header check required here.
+	 */
+	if (image_get_magic(header) != IH_MAGIC) {
+		puts("hdr fail");
+		return -EFAULT;
+	}
+
 	ret = spl_parse_image_header(header);
 	if (ret)
 		return ret;
 
+	puts("hdr ok");
+
+	/* TODO: This assumes a header is present (e.g. no PPC images) */
+	/* Could also check spl_image.flags & SPL_COPY_PAYLOAD_ONLY above */
+
+	image_size_bytes = __be32_to_cpu(header->ih_size);
+	data_crc = __be32_to_cpu(header->ih_dcrc);
+
+	if ((image_size_bytes < UBOOT_MIN_SIZE_BYTES) || (image_size_bytes > UBOOT_MAX_SIZE_BYTES)) {
+		puts(", data len fail");
+		return -EFAULT;
+	}
+
+	puts(", data len ok");
+
 	/* convert size to sectors - round up */
 	image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) /
 			     mmc->read_bl_len;
@@ -36,10 +182,22 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 	/* Read the header too to avoid extra memcpy */
 	count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
 			  (void *)(ulong)spl_image.load_addr);
+
 	debug("read %x sectors to %x\n", image_size_sectors,
 	      spl_image.load_addr);
-	if (count != image_size_sectors)
+	if (count != image_size_sectors) {
+		puts(", read error");
 		return -EIO;
+	}
+
+	/* Check data CRC */
+	data_crc_memory = crc32(0, (const u8*)(spl_image.load_addr + header_size), image_size_bytes);
+	if (data_crc_memory != data_crc) {
+		puts(", data crc fail");
+		return -EFAULT;
+	}
+
+	puts(", data crc ok");
 
 	return 0;
 }
@@ -58,6 +216,8 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 	struct image_header *header;
 	int ret = 0;
 
+	printf("Checking U-Boot at sector 0x%lx: ", sector);
+
 	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
 					 sizeof(struct image_header));
 
@@ -65,6 +225,11 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
 	debug("hdr read sector %lx, count=%lu\n", sector, count);
 	if (count == 0) {
+/*
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+		puts("mmc_load_image_raw_sector: mmc block read error\n");
+#endif
+*/
 		ret = -EIO;
 		goto end;
 	}
@@ -86,12 +251,12 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 
 end:
 	if (ret) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		puts("mmc_load_image_raw_sector: mmc block read error\n");
-#endif
+		puts(" -> skipping\n");
 		return -1;
 	}
 
+	puts("\n");
+
 	return 0;
 }
 
@@ -321,11 +486,36 @@ int spl_mmc_load_image(u32 boot_device)
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION);
 		if (!err)
 			return err;
+
 #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR)
+
+#if defined(CONFIG_NM_BOOTLOADER_FORMAT)
+		/* Try to load NetModule packed bootloader from main location */
+		err = mmc_load_image_raw_sector_netmodule(mmc,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+		if (!err)
+			return err;	/* found -> ok */
+#endif
+		/* Try to load bootloader from main location */
 		err = mmc_load_image_raw_sector(mmc,
 			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
 		if (!err)
-			return err;
+			return err;	/* found -> ok */
+
+#if defined(CONFIG_NM_BOOTLOADER_FORMAT)
+		/* Try to load NetModule packed bootloader from alternate location */
+		err = mmc_load_image_raw_sector_netmodule(mmc,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_ALTERNATE);
+		if (!err)
+			return err;	/* found -> ok */
+#endif
+
+		/* Try to load regular bootloader from alternate location */
+		err = mmc_load_image_raw_sector(mmc,
+			CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR_ALTERNATE);
+		if (!err) {
+			return err;	/* found -> ok */
+		}
 #endif
 		/* If RAW mode fails, try FS mode. */
 	case MMCSD_MODE_FS:

common/xyzModem.c

@@ -60,9 +60,9 @@ static struct
 #endif
 } xyz;
 
-#define xyzModem_CHAR_TIMEOUT            2000	/* 2 seconds */
-#define xyzModem_MAX_RETRIES             20
-#define xyzModem_MAX_RETRIES_WITH_CRC    10
+#define xyzModem_CHAR_TIMEOUT            200	/* 0.2 seconds */
+#define xyzModem_MAX_RETRIES             200
+#define xyzModem_MAX_RETRIES_WITH_CRC    100
 #define xyzModem_CAN_COUNT                3	/* Wait for 3 CAN before quitting */
 
 
@@ -379,7 +379,7 @@ xyzModem_get_hdr (void)
 	  /* Data stream timed out */
 	  xyzModem_flush ();	/* Toss any current input */
 	  ZM_DEBUG (zm_dump (__LINE__));
-	  CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);
+	  /*CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000);*/
 	  return xyzModem_timeout;
 	}
     }
@@ -563,7 +563,7 @@ xyzModem_stream_open (connection_info_t * info, int *err)
 	{
 	  if (--crc_retries <= 0)
 	    xyz.crc_mode = false;
-	  CYGACC_CALL_IF_DELAY_US (5 * 100000);	/* Extra delay for startup */
+	  /*CYGACC_CALL_IF_DELAY_US (5 * 100000);*/	/* Extra delay for startup */
 	  CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK));
 	  xyz.total_retries++;
 	  ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__));

configs/am335x_hw25_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_HW25=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+# CONFIG_BOOTP_PXE_CLIENTARCH is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_FPGA is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_PMIC is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set

configs/am335x_nbhw16_defconfig

@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NETBIRD=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y

configs/am335x_nbhw16_v2_defconfig

@@ -0,0 +1,631 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# U-Boot 2016.05 Configuration
+#
+CONFIG_CREATE_ARCH_SYMLINK=y
+# CONFIG_ARC is not set
+CONFIG_ARM=y
+# CONFIG_AVR32 is not set
+# CONFIG_BLACKFIN is not set
+# CONFIG_M68K is not set
+# CONFIG_MICROBLAZE is not set
+# CONFIG_MIPS is not set
+# CONFIG_NDS32 is not set
+# CONFIG_NIOS2 is not set
+# CONFIG_OPENRISC is not set
+# CONFIG_PPC is not set
+# CONFIG_SANDBOX is not set
+# CONFIG_SH is not set
+# CONFIG_SPARC is not set
+# CONFIG_X86 is not set
+CONFIG_SYS_ARCH="arm"
+CONFIG_SYS_CPU="armv7"
+CONFIG_SYS_SOC="am33xx"
+CONFIG_SYS_VENDOR="nm"
+CONFIG_SYS_BOARD="netbird_v2"
+CONFIG_SYS_CONFIG_NAME="am335x_netbird_v2"
+
+#
+# ARM architecture
+#
+CONFIG_HAS_VBAR=y
+CONFIG_HAS_THUMB2=y
+CONFIG_CPU_V7=y
+# CONFIG_SEMIHOSTING is not set
+# CONFIG_SYS_L2CACHE_OFF is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_TARGET_EDB93XX is not set
+# CONFIG_TARGET_VCMA9 is not set
+# CONFIG_TARGET_SMDK2410 is not set
+# CONFIG_TARGET_ASPENITE is not set
+# CONFIG_TARGET_GPLUGD is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_KIRKWOOD is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_TARGET_DEVKIT3250 is not set
+# CONFIG_TARGET_WORK_92105 is not set
+# CONFIG_TARGET_MX25PDK is not set
+# CONFIG_TARGET_ZMX25 is not set
+# CONFIG_TARGET_APF27 is not set
+# CONFIG_TARGET_APX4DEVKIT is not set
+# CONFIG_TARGET_XFI3 is not set
+# CONFIG_TARGET_M28EVK is not set
+# CONFIG_TARGET_MX23EVK is not set
+# CONFIG_TARGET_MX28EVK is not set
+# CONFIG_TARGET_MX23_OLINUXINO is not set
+# CONFIG_TARGET_BG0900 is not set
+# CONFIG_TARGET_SANSA_FUZE_PLUS is not set
+# CONFIG_TARGET_SC_SPS_1 is not set
+# CONFIG_ORION5X is not set
+# CONFIG_TARGET_SPEAR300 is not set
+# CONFIG_TARGET_SPEAR310 is not set
+# CONFIG_TARGET_SPEAR320 is not set
+# CONFIG_TARGET_SPEAR600 is not set
+# CONFIG_TARGET_STV0991 is not set
+# CONFIG_TARGET_X600 is not set
+# CONFIG_TARGET_IMX31_PHYCORE is not set
+# CONFIG_TARGET_MX31ADS is not set
+# CONFIG_TARGET_MX31PDK is not set
+# CONFIG_TARGET_WOODBURN is not set
+# CONFIG_TARGET_WOODBURN_SD is not set
+# CONFIG_TARGET_FLEA3 is not set
+# CONFIG_TARGET_MX35PDK is not set
+# CONFIG_ARCH_BCM283X is not set
+# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
+# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
+# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
+# CONFIG_TARGET_KWB is not set
+# CONFIG_TARGET_TSERIES is not set
+# CONFIG_TARGET_CM_T335 is not set
+# CONFIG_TARGET_PEPPER is not set
+# CONFIG_TARGET_AM335X_IGEP0033 is not set
+# CONFIG_TARGET_PCM051 is not set
+# CONFIG_TARGET_DRACO is not set
+# CONFIG_TARGET_THUBAN is not set
+# CONFIG_TARGET_RASTABAN is not set
+# CONFIG_TARGET_PXM2 is not set
+# CONFIG_TARGET_RUT is not set
+# CONFIG_TARGET_PENGWYN is not set
+# CONFIG_TARGET_AM335X_BALTOS is not set
+# CONFIG_TARGET_AM335X_EVM is not set
+# CONFIG_TARGET_AM335X_NETBIRD is not set
+CONFIG_TARGET_AM335X_NETBIRD_V2=y
+# CONFIG_TARGET_AM335X_SL50 is not set
+# CONFIG_TARGET_BAV335X is not set
+# CONFIG_TARGET_TI814X_EVM is not set
+# CONFIG_TARGET_TI816X_EVM is not set
+# CONFIG_TARGET_BCM28155_AP is not set
+# CONFIG_TARGET_BCMCYGNUS is not set
+# CONFIG_TARGET_BCMNSP is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_KEYSTONE is not set
+# CONFIG_ARCH_MESON is not set
+# CONFIG_ARCH_MX7 is not set
+# CONFIG_ARCH_MX6 is not set
+# CONFIG_ARCH_MX5 is not set
+# CONFIG_TARGET_M53EVK is not set
+# CONFIG_TARGET_MX51EVK is not set
+# CONFIG_TARGET_MX53ARD is not set
+# CONFIG_TARGET_MX53EVK is not set
+# CONFIG_TARGET_MX53LOCO is not set
+# CONFIG_TARGET_MX53SMD is not set
+# CONFIG_OMAP34XX is not set
+# CONFIG_OMAP44XX is not set
+# CONFIG_OMAP54XX is not set
+# CONFIG_AM43XX is not set
+# CONFIG_RMOBILE is not set
+# CONFIG_ARCH_SNAPDRAGON is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_TARGET_CM_T43 is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_TARGET_TS4800 is not set
+# CONFIG_TARGET_VF610TWR is not set
+# CONFIG_TARGET_COLIBRI_VF is not set
+# CONFIG_TARGET_PCM052 is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_ARCH_ZYNQMP is not set
+# CONFIG_TEGRA is not set
+# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
+# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set
+# CONFIG_TARGET_VEXPRESS64_JUNO is not set
+# CONFIG_TARGET_LS2080A_EMU is not set
+# CONFIG_TARGET_LS2080A_SIMU is not set
+# CONFIG_TARGET_LS2080AQDS is not set
+# CONFIG_TARGET_LS2080ARDB is not set
+# CONFIG_TARGET_HIKEY is not set
+# CONFIG_TARGET_LS1021AQDS is not set
+# CONFIG_TARGET_LS1021ATWR is not set
+# CONFIG_TARGET_LS1043AQDS is not set
+# CONFIG_TARGET_LS1043ARDB is not set
+# CONFIG_TARGET_H2200 is not set
+# CONFIG_TARGET_ZIPITZ2 is not set
+# CONFIG_TARGET_COLIBRI_PXA270 is not set
+# CONFIG_ARCH_UNIPHIER is not set
+# CONFIG_STM32 is not set
+# CONFIG_ARCH_ROCKCHIP is not set
+# CONFIG_TARGET_THUNDERX_88XX is not set
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_CONS_INDEX=2
+CONFIG_SYS_MALLOC_F=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+# CONFIG_SPL_DM is not set
+CONFIG_DM_SERIAL=y
+# CONFIG_DM_SPI is not set
+# CONFIG_DM_I2C is not set
+CONFIG_DM_GPIO=y
+# CONFIG_BLK is not set
+# CONFIG_ARMV7_LPAE is not set
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+
+#
+# ARM debug
+#
+# CONFIG_DEBUG_LL is not set
+# CONFIG_DM_KEYBOARD is not set
+# CONFIG_AHCI is not set
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
+
+#
+# Boot images
+#
+CONFIG_SUPPORT_SPL=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+# CONFIG_SPL_SEPARATE_BSS is not set
+CONFIG_FIT=y
+# CONFIG_FIT_VERBOSE is not set
+# CONFIG_FIT_SIGNATURE is not set
+# CONFIG_FIT_BEST_MATCH is not set
+# CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_OF_SYSTEM_SETUP is not set
+# CONFIG_OF_STDOUT_VIA_ALIAS is not set
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+# CONFIG_SPL_LOAD_FIT is not set
+
+#
+# Boot timing
+#
+# CONFIG_BOOTSTAGE is not set
+CONFIG_BOOTSTAGE_USER_COUNT=20
+CONFIG_BOOTSTAGE_STASH_ADDR=0
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+# CONFIG_CONSOLE_RECORD is not set
+
+#
+# Command line interface
+#
+CONFIG_CMDLINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="=> "
+
+#
+# Autoboot options
+#
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+# CONFIG_AUTOBOOT_ENCRYPTION is not set
+CONFIG_AUTOBOOT_DELAY_STR=""
+CONFIG_AUTOBOOT_STOP_STR="s"
+# CONFIG_AUTOBOOT_KEYED_CTRLC is not set
+
+#
+# Commands
+#
+
+#
+# Info commands
+#
+CONFIG_CMD_BDI=y
+CONFIG_CMD_CONSOLE=y
+# CONFIG_CMD_CPU is not set
+# CONFIG_CMD_LICENSE is not set
+
+#
+# Boot commands
+#
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_FDT=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_RUN=y
+CONFIG_CMD_IMI=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+
+#
+# Environment commands
+#
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EXPORTENV=y
+CONFIG_CMD_IMPORTENV=y
+CONFIG_CMD_EDITENV=y
+# CONFIG_CMD_GREPENV is not set
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_ENV_EXISTS=y
+
+#
+# Memory commands
+#
+CONFIG_CMD_MEMORY=y
+CONFIG_CMD_CRC32=y
+# CONFIG_LOOPW is not set
+# CONFIG_CMD_MEMTEST is not set
+# CONFIG_CMD_MX_CYCLIC is not set
+# CONFIG_CMD_MEMINFO is not set
+
+#
+# Device access commands
+#
+CONFIG_CMD_DM=y
+# CONFIG_CMD_DEMO is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_ARMFLASH is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_NAND is not set
+# CONFIG_CMD_SF is not set
+# CONFIG_CMD_SPI is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_DFU is not set
+# CONFIG_CMD_USB_MASS_STORAGE is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_GPIO is not set
+
+#
+# Shell scripting commands
+#
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_SOURCE=y
+# CONFIG_CMD_SETEXPR is not set
+
+#
+# Network commands
+#
+CONFIG_CMD_NET=y
+# CONFIG_CMD_TFTPPUT is not set
+# CONFIG_CMD_TFTPSRV is not set
+# CONFIG_CMD_RARP is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_CDP is not set
+# CONFIG_CMD_SNTP is not set
+# CONFIG_CMD_DNS is not set
+# CONFIG_CMD_LINK_LOCAL is not set
+
+#
+# Misc commands
+#
+# CONFIG_CMD_CACHE is not set
+# CONFIG_CMD_TIME is not set
+CONFIG_CMD_MISC=y
+# CONFIG_CMD_TIMER is not set
+# CONFIG_CMD_QFW is not set
+
+#
+# Power commands
+#
+
+#
+# Security commands
+#
+
+#
+# Filesystem commands
+#
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SUPPORT_OF_CONTROL=y
+
+#
+# Device Tree Control
+#
+# CONFIG_OF_CONTROL is not set
+CONFIG_NET=y
+# CONFIG_NET_RANDOM_ETHADDR is not set
+# CONFIG_NETCONSOLE is not set
+CONFIG_NET_TFTP_VARS=y
+CONFIG_BOOTP_PXE_CLIENTARCH=0x15
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_DM=y
+CONFIG_DM_WARN=y
+CONFIG_DM_DEVICE_REMOVE=y
+CONFIG_DM_STDIO=y
+CONFIG_DM_SEQ_ALIAS=y
+# CONFIG_SPL_DM_SEQ_ALIAS is not set
+# CONFIG_REGMAP is not set
+# CONFIG_SPL_REGMAP is not set
+# CONFIG_DEVRES is not set
+# CONFIG_ADC is not set
+# CONFIG_ADC_EXYNOS is not set
+# CONFIG_ADC_SANDBOX is not set
+# CONFIG_BLOCK_CACHE is not set
+
+#
+# Clock
+#
+# CONFIG_CLK is not set
+# CONFIG_CPU is not set
+
+#
+# Hardware crypto devices
+#
+# CONFIG_FSL_CAAM is not set
+
+#
+# Demo for driver model
+#
+# CONFIG_DM_DEMO is not set
+
+#
+# DFU support
+#
+CONFIG_DFU_TFTP=y
+
+#
+# DMA Support
+#
+# CONFIG_DMA is not set
+# CONFIG_TI_EDMA3 is not set
+
+#
+# GPIO Support
+#
+# CONFIG_ALTERA_PIO is not set
+# CONFIG_DWAPB_GPIO is not set
+# CONFIG_ATMEL_PIO4 is not set
+# CONFIG_INTEL_BROADWELL_GPIO is not set
+# CONFIG_LPC32XX_GPIO is not set
+# CONFIG_MSM_GPIO is not set
+# CONFIG_ROCKCHIP_GPIO is not set
+# CONFIG_VYBRID_GPIO is not set
+# CONFIG_DM_74X164 is not set
+# CONFIG_DM_PCA953X is not set
+
+#
+# I2C support
+#
+# CONFIG_DM_I2C_COMPAT is not set
+# CONFIG_SYS_I2C_DW is not set
+# CONFIG_CROS_EC_KEYB is not set
+
+#
+# LED Support
+#
+# CONFIG_LED is not set
+
+#
+# Mailbox Controller Support
+#
+
+#
+# Memory Controller drivers
+#
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MISC is not set
+# CONFIG_CROS_EC is not set
+# CONFIG_FSL_SEC_MON is not set
+# CONFIG_MXC_OCOTP is not set
+# CONFIG_PWRSEQ is not set
+# CONFIG_PCA9551_LED is not set
+# CONFIG_SYSRESET is not set
+# CONFIG_WINBOND_W83627 is not set
+
+#
+# MMC Host controller Support
+#
+# CONFIG_DM_MMC is not set
+
+#
+# MTD Support
+#
+# CONFIG_MTD is not set
+
+#
+# NAND Device Support
+#
+# CONFIG_NAND_DENALI is not set
+# CONFIG_NAND_VF610_NFC is not set
+# CONFIG_NAND_PXA3XX is not set
+# CONFIG_NAND_ARASAN is not set
+
+#
+# Generic NAND options
+#
+# CONFIG_SPL_NAND_DENALI is not set
+
+#
+# SPI Flash Support
+#
+# CONFIG_SPI_FLASH is not set
+# CONFIG_DM_ETH is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_NETDEVICES is not set
+
+#
+# PCI
+#
+# CONFIG_DM_PCI is not set
+
+#
+# Pin controllers
+#
+# CONFIG_PINCTRL is not set
+
+#
+# Power
+#
+# CONFIG_DM_PMIC is not set
+# CONFIG_DM_REGULATOR is not set
+# CONFIG_DM_PWM is not set
+# CONFIG_RAM is not set
+
+#
+# Remote Processor drivers
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_DM_RTC is not set
+
+#
+# Serial drivers
+#
+CONFIG_REQUIRE_SERIAL_CONSOLE=y
+CONFIG_SERIAL_PRESENT=y
+CONFIG_SPL_SERIAL_PRESENT=y
+# CONFIG_DEBUG_UART is not set
+# CONFIG_DEBUG_UART_SKIP_INIT is not set
+# CONFIG_ALTERA_JTAG_UART is not set
+# CONFIG_ALTERA_UART is not set
+# CONFIG_FSL_LPUART is not set
+CONFIG_SYS_NS16550=y
+# CONFIG_MSM_SERIAL is not set
+
+#
+# Sound support
+#
+# CONFIG_SOUND is not set
+
+#
+# SPI Support
+#
+# CONFIG_FSL_ESPI is not set
+# CONFIG_TI_QSPI is not set
+
+#
+# SPMI support
+#
+# CONFIG_SPMI is not set
+# CONFIG_DM_THERMAL is not set
+
+#
+# Timer Support
+#
+# CONFIG_TIMER is not set
+
+#
+# TPM support
+#
+CONFIG_USB=y
+# CONFIG_DM_USB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_XHCI is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_EHCI is not set
+# CONFIG_USB_DWC3 is not set
+
+#
+# MUSB Controller Driver
+#
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+
+#
+# ULPI drivers
+#
+
+#
+# USB peripherals
+#
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_KEYBOARD is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_DWC2_OTG is not set
+# CONFIG_CI_UDC is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+
+#
+# Graphics support
+#
+# CONFIG_DM_VIDEO is not set
+
+#
+# TrueType Fonts
+#
+# CONFIG_VIDEO_VESA is not set
+# CONFIG_VIDEO_LCD_ANX9804 is not set
+# CONFIG_VIDEO_LCD_SSD2828 is not set
+# CONFIG_VIDEO_MVEBU is not set
+# CONFIG_DISPLAY is not set
+# CONFIG_VIDEO_BRIDGE is not set
+# CONFIG_PHYS_TO_BUS is not set
+
+#
+# File systems
+#
+
+#
+# Library routines
+#
+# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
+CONFIG_HAVE_PRIVATE_LIBGCC=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
+CONFIG_SYS_HZ=1000
+# CONFIG_USE_TINY_PRINTF is not set
+CONFIG_REGEX=y
+# CONFIG_LIB_RAND is not set
+# CONFIG_CMD_DHRYSTONE is not set
+# CONFIG_RSA is not set
+# CONFIG_TPM is not set
+
+#
+# Hashing Support
+#
+# CONFIG_SHA1 is not set
+# CONFIG_SHA256 is not set
+# CONFIG_SHA_HW_ACCEL is not set
+
+#
+# Compression Support
+#
+# CONFIG_LZ4 is not set
+# CONFIG_ERRNO_STR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_SPL_OF_LIBFDT is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_UNIT_TEST is not set

configs/am335x_netbird_v2_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NETBIRD_V2=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+# CONFIG_BOOTP_PXE_CLIENTARCH is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_FPGA is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_PMIC is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set